A semiconductor memory device may include a core circuit including a plurality of memory cell arrays electrically connected between a plurality of row lines and a plurality of column lines, and a column path control circuit configured to generate a preliminary column pulse from a command signal irrelevant to a column address signal, to generate a main column pulse in response to an enable time point of the column address signal and an enable time point of the preliminary column pulse, and to enable an access target column line among the plurality of column lines.

A memory device includes a plurality of word lines elongated along a first direction, and at least one memory unit. The at least one memory unit includes a plurality of memory cells, at least one bit line, and at least one column word line. The plurality of memory cells are arranged along a second direction different from the first direction. The at least one bit line is elongated along the second direction, and configured to transmit data of a selected memory cell. The at least one column word line is elongated along the second direction, and configured to control electrical connections between the memory cells and the at least one bit line, wherein the selected memory cell is selected by a corresponding word line and the at least one column word line.

The present disclosure includes apparatuses and methods related to an artificial intelligence accelerator in memory. An example apparatus can include a number of registers configured to enable the apparatus to operate in an artificial intelligence mode to perform artificial intelligence operations and an artificial intelligence (AI) accelerator configured to perform the artificial intelligence operations using the data stored in the number of memory arrays. The AI accelerator can include hardware, software, and or firmware that is configured to perform operations associated with AI operations. The hardware can include circuitry configured as an adder and/or multiplier to perform operations, such as logic operations, associated with AI operations.

A semiconductor device includes a memory core circuit configured to generate core data from bank data outputted by a bank or generate the core data from a dummy column address based on a read operation for the bank. The semiconductor device also includes a data control circuit configured to generate a switching signal from a bank active signal or a dummy bank address based on the read operation for the bank and and configured to control the output of the core data based on the switching signal.

Methods, systems, and devices for managing memory based on access duration are described. A memory device may include a first set of memory cells resilient against access durations of a first duration and a second set of memory cells resilient against access durations of a shorter duration. A command for accessing the memory device may be received. The command may be associated with an access duration. Whether to access, as part of executing the command, the first set of memory cells or the second set of memory cells may be determined based on the access duration. The first set of memory cells may be accessed, as part of executing the command, based on the access duration being greater than a threshold duration. Or the second set of memory cells may be accessed based on the access duration being less than or equal to the threshold duration.

An electronic system includes a controller configured to detect a bank in a standby state for a write operation between a first bank and a second bank during a refresh operation period and output data for performing a post-write operation to the bank in the standby state for the write operation. The electronic system also includes an electronic device including the first and second banks. The electronic device is configured to latch the data in an input/output control circuit connected to the bank in the standby state for the write operation.

A semiconductor memory is provided. The memory includes: a memory array; a row address processing unit configured to output a row address; a bank address processing unit configured to output a bank address; a column address processing unit configured to output a column address; and a mapping factor generating unit, configured to generate a mapping factor, wherein an output of the mapping factor generating unit is coupled to at least one of an output of the row address processing unit, an output of the bank address processing unit, and an output of the column address processing unit, and the output of the mapping factor generating unit is further coupled to the memory array, and wherein the memory array receives a result from logical processing performed on the mapping factor and at least one of the row address, the bank address, and the column address. The technical solutions of the embodiments of the present invention can improve the security, service life and reliability of the semiconductor memory.

A semiconductor memory is provided. The memory includes: a memory array; a row address processing unit configured to output a row address; a bank address processing unit configured to output a bank address; a column address processing unit configured to output a column address; and a mapping factor generating unit, configured to generate a mapping factor, wherein an output of the mapping factor generating unit is coupled to at least one of an output of the row address processing unit, an output of the bank address processing unit, and an output of the column address processing unit, and the output of the mapping factor generating unit is further coupled to the memory array, and wherein the memory array receives a result from logical processing performed on the mapping factor and at least one of the row address, the bank address, and the column address. The technical solutions of the embodiments of the present invention can improve the security, service life and reliability of the semiconductor memory.

Technology is disclosed herein for concurrently programming the same data pattern in multiple sets of non-volatile memory cells. Voltage are applied to bit lines in accordance with a data pattern. A select voltage is applied to drain select gates of multiple sets of NAND strings. The system concurrently applies a program pulse to control gates of a different set of selected memory cells in each respective set of the multiple sets of the NAND strings while the select voltage is applied to the drain select gates of the multiple sets of the NAND strings and the voltages are applied to the plurality of bit lines to concurrently program the data pattern into each set of the selected memory cells.

Technology is disclosed herein for concurrently programming the same data pattern in multiple sets of non-volatile memory cells. Voltage are applied to bit lines in accordance with a data pattern. A select voltage is applied to drain select gates of multiple sets of NAND strings. The system concurrently applies a program pulse to control gates of a different set of selected memory cells in each respective set of the multiple sets of the NAND strings while the select voltage is applied to the drain select gates of the multiple sets of the NAND strings and the voltages are applied to the plurality of bit lines to concurrently program the data pattern into each set of the selected memory cells.