A nonvolatile memory device includes a memory cell array and a row decoder. The memory cell array includes a plurality of mats. A first cell string of first mat is connected to a plurality of first word-lines, a first bit-line and a first string selection line. A second cell string of second mat is connected to a plurality of second word-lines, a second bit-line and a second string selection line. Each of the first and second cell strings includes a ground selection transistor, memory cells, and a string selection transistor coupled in series. The row decoder applies a first voltage to a third word-line among the plurality of first and second word-lines for a first period of time in a single mat mode and to apply a second voltage to the third word-line for a second period of time longer than the first period of time in a multi-mat mode.

A nonvolatile memory device includes a memory cell array and a row decoder. The memory cell array includes a plurality of mats. A first cell string of first mat is connected to a plurality of first word-lines, a first bit-line and a first string selection line. A second cell string of second mat is connected to a plurality of second word-lines, a second bit-line and a second string selection line. Each of the first and second cell strings includes a ground selection transistor, memory cells, and a string selection transistor coupled in series. The row decoder applies a first voltage to a third word-line among the plurality of first and second word-lines for a first period of time in a single mat mode and to apply a second voltage to the third word-line for a second period of time longer than the first period of time in a multi-mat mode.

An interconnected stack of Dynamic Random Access Memory (DRAM) die has a base die and DRAM dies. The base die is interconnected vertically with the DRAM dies using through-silicon via (TSV) connections that carry data and control signals throughout the stack. The data signals of the DRAM dies are interconnected vertically to the base die using separate, non-overlapping, sets of TSVs. In a first configuration, each die in the stack is accessed using unique chip identification numbers. In a second configuration, a single chip identification number is used to access two or more dies in the stack. At least one bit of the chip identification number may be used in determining the row being accessed. Data communicated with dies in the stack may be communicated with the base die using non-overlapping sets of data signal connections.

An interconnected stack of Dynamic Random Access Memory (DRAM) die has a base die and DRAM dies. The base die is interconnected vertically with the DRAM dies using through-silicon via (TSV) connections that carry data and control signals throughout the stack. The data signals of the DRAM dies are interconnected vertically to the base die using separate, non-overlapping, sets of TSVs. In a first configuration, each die in the stack is accessed using unique chip identification numbers. In a second configuration, a single chip identification number is used to access two or more dies in the stack. At least one bit of the chip identification number may be used in determining the row being accessed. Data communicated with dies in the stack may be communicated with the base die using non-overlapping sets of data signal connections.

An example of an apparatus may include memory organized as at least one bank that includes two or more arrays, and circuitry communicatively coupled to the memory to select respective rows of the two or more arrays of a bank for a memory access operation based on an access orientation signal. Other examples are disclosed and claimed.

A semiconductor device includes a read write control circuit configured to generate first and second write command pulses from an external control signal for performing a write operation; a flag generation circuit configured to generate a write flag, a write shifting flag, an internal write flag and an internal write shifting flag based on the second write command pulse, a bank mode signal and a bank group mode signal; and a bank group selection signal generation circuit configured to store a bank address based on an write input control pulse generated from the second write command pulse in a bank mode, and output the stored bank address as a bank group selection signal based on a write output control pulse generated from the write flag.

An electronic device includes a shifting circuit and a dock repeater. The shifting circuit is configured to generate a write shifting flag that is inactivated when a write signal for a write operation is activated. The clock repeater is configured to block generation of a read repeating dock that is used in a read operation when the write shifting flag is inactivated.

An electronic device includes a shifting circuit and a dock repeater. The shifting circuit is configured to generate a write shifting flag that is inactivated when a write signal for a write operation is activated. The clock repeater is configured to block generation of a read repeating dock that is used in a read operation when the write shifting flag is inactivated.

A system includes a memory device to maintain data for a machine learning operation. The memory device includes solder balls. The system further includes a machine learning processing device to perform the machine learning operation. The system further includes a processing device to select, based on the machine learning operation, a set of solder balls from the plurality of solder balls to transmit the data from the non-volatile memory device to the machine learning processing device.

A semiconductor device includes a controller circuit and a signal generating circuit. The controller circuit is coupled to a plurality of memory devices and configured to generate a plurality of chip enable signals. One of the chip enable signals is provided to one of the memory devices, so as to respectively enable the corresponding memory device. The signal generating circuit is disposed outside of the controller circuit and configured to receive the chip enable signals and generate a termination circuit enable signal according to the chip enable signals. The termination circuit enable signal is provided to the memory devices. When a state of any of the chip enable signals is set to an enabled state, a state of the termination circuit enable signal generated by the signal generating circuit is set to an enabled state.