Technology is disclosed herein for concurrently programming the same data pattern in multiple sets of non-volatile memory cells. Voltage are applied to bit lines in accordance with a data pattern. A select voltage is applied to drain select gates of multiple sets of NAND strings. The system concurrently applies a program pulse to control gates of a different set of selected memory cells in each respective set of the multiple sets of the NAND strings while the select voltage is applied to the drain select gates of the multiple sets of the NAND strings and the voltages are applied to the plurality of bit lines to concurrently program the data pattern into each set of the selected memory cells.

Technology is disclosed herein for concurrently programming the same data pattern in multiple sets of non-volatile memory cells. Voltage are applied to bit lines in accordance with a data pattern. A select voltage is applied to drain select gates of multiple sets of NAND strings. The system concurrently applies a program pulse to control gates of a different set of selected memory cells in each respective set of the multiple sets of the NAND strings while the select voltage is applied to the drain select gates of the multiple sets of the NAND strings and the voltages are applied to the plurality of bit lines to concurrently program the data pattern into each set of the selected memory cells.

A memory device in accordance with a described method of operation includes a read only memory (ROM) address controller and a suspend signal generator. The ROM address controller is configured to sequentially output a plurality of operation ROM addresses at which ROM codes to be executed in response to an operation command are stored, and to suspend output of the plurality of operation ROM addresses in response to a suspend signal. The suspend signal generator is configured to generate the suspend signal that is activated during a preset period depending on whether a suspend ROM address is identical to an operation ROM address, among the plurality of operation ROM addresses, currently being output. The suspend ROM address is an address at which a ROM code, execution of which is to be suspended, among the ROM codes, is stored.

A voltage regulator and a semiconductor memory device having the same are disclosed. The voltage regulator includes an amplifier configured to amplify a difference between a reference voltage and a feedback voltage to generate an amplifier output voltage, a voltage feedback unit connected between an output supply voltage generation node and a ground voltage and configured to generate the feedback voltage, a first transfer gate unit connected between an input supply voltage and the voltage generation node and driven in response to the amplifier output voltage to provide first current, a current load replica unit connected between the voltage generation node and the ground voltage and configured to consume the first current, and a transfer unit connected between the input supply voltage and the voltage generation node and driven in response to the amplifier output voltage when the current load unit performs an operation, to provide second current.

A voltage regulator and a semiconductor memory device having the same are disclosed. The voltage regulator includes an amplifier configured to amplify a difference between a reference voltage and a feedback voltage to generate an amplifier output voltage, a voltage feedback unit connected between an output supply voltage generation node and a ground voltage and configured to generate the feedback voltage, a first transfer gate unit connected between an input supply voltage and the voltage generation node and driven in response to the amplifier output voltage to provide first current, a current load replica unit connected between the voltage generation node and the ground voltage and configured to consume the first current, and a transfer unit connected between the input supply voltage and the voltage generation node and driven in response to the amplifier output voltage when the current load unit performs an operation, to provide second current.

A method of operating a memory device includes receiving a duty training request, performing first training for a write path in a first period, storing a result value of the first training, performing second training for a write path in a second period, storing a result value of the second training, transmitting the result value of the first training to an external device, and receiving a duty cycle adjuster (DCA) code value corresponding to the first training result value from the external device.

A method of operating a memory device includes receiving a duty training request, performing first training for a write path in a first period, storing a result value of the first training, performing second training for a write path in a second period, storing a result value of the second training, transmitting the result value of the first training to an external device, and receiving a duty cycle adjuster (DCA) code value corresponding to the first training result value from the external device.

There are provided a memory system and an operating method of the memory system. The memory system includes: a main controller for transmitting main data having N bits through a main channel, where N is a positive integer; memory devices for storing sub-data constituting the main data, and transmitting the sub-data through sub-channels; and a sub-controller for communicating with the main controller through the main channel, and communicating with the memory devices through the sub-channels. The sub-controller generates the sub-data each having n bits where n is a positive integer less than N, by dividing the main data, generates sub-data strobe clocks by decreasing a frequency of a main data strobe clock synchronized with the main data, and transmits/receives the sub-data to/from the memory devices in synchronization with the sub-data strobe clocks.

There are provided a memory system and an operating method of the memory system. The memory system includes: a main controller for transmitting main data having N bits through a main channel, where N is a positive integer; memory devices for storing sub-data constituting the main data, and transmitting the sub-data through sub-channels; and a sub-controller for communicating with the main controller through the main channel, and communicating with the memory devices through the sub-channels. The sub-controller generates the sub-data each having n bits where n is a positive integer less than N, by dividing the main data, generates sub-data strobe clocks by decreasing a frequency of a main data strobe clock synchronized with the main data, and transmits/receives the sub-data to/from the memory devices in synchronization with the sub-data strobe clocks.

Memory array circuits including word line circuits providing word line signal stability are disclosed. In a memory access operation, the states of word line signals on word lines in the memory rows of the memory array may be based on the states of word line latches during a first clock state of a latch clock signal. The word line latches receive address decode signals generated from a decoded memory address. An inverted delay clock circuit generates a clock pulse from the latch clock signal. The word line latches store the address decode signals during the clock pulse and generate word line signals based on the stored address decode signals. The memory address is received from an address bus. Pass-through address capture latches maximize time available to a decoder for decoding the memory address and word line latches reduce fluctuations in the address signal being propagated to the word line signals.