Apparatuses, systems, and methods for row hammer based cache lockdown. A controller of a memory may include an aggressor detector circuit which determines if addresses are aggressor addresses or not. The controller may include a tracker circuit which may count a number of times an address is identified as an aggressor, and may determine if the aggressor address is a frequent aggressor address based on the count. If the address is a frequent aggressor address, a cache entry associated with the frequent aggressor address may be locked (e.g., for a set amount of time). In some embodiments, the controller may include a second tracker which may determine if the frequent aggressor address is a highly attacked address. An address mapping associated with the highly attacked address may be changed.

Devices are disclosed. A device may include a source configured to couple to a number of memory cells. The device may also include at least one transistor coupled between the source and a ground voltage. Further, the device may include an antifuse coupled between the at least one transistor and the ground voltage. Methods and systems are also disclosed.

Devices are disclosed. A device may include a source configured to couple to a number of memory cells. The device may also include at least one transistor coupled between the source and a ground voltage. Further, the device may include an antifuse coupled between the at least one transistor and the ground voltage. Methods and systems are also disclosed.

A memory device, memory address decoder, a memory system and related method for memory attack detection are disclosed. An apparatus includes a memory decoder include multiple stages in a decoding path configured to generate a select signal from an input address signal, and fault detecting logic operably coupled with the memory decoder and configured to receive feedback signals distributed from the multiple stages indicative of a fault along the decoding path.

A memory device, memory address decoder, a memory system and related method for memory attack detection are disclosed. An apparatus includes a memory decoder include multiple stages in a decoding path configured to generate a select signal from an input address signal, and fault detecting logic operably coupled with the memory decoder and configured to receive feedback signals distributed from the multiple stages indicative of a fault along the decoding path.

Systems, apparatuses, and methods related to a computer system having a page table entry containing permission bits for predefined types of memory accesses made by executions of routines in predefined domains are described. The page table entry can be used to map a virtual memory address to a physical memory address. In response to a routine accessing the virtual memory address, a permission bit corresponding to the execution domain of the routine and a type of the memory access can be extracted from the page table entry to determine whether the memory access is to be rejected.

Systems, apparatuses, and methods related to a computer system having a page table entry containing permission bits for predefined types of memory accesses made by executions of routines in predefined domains are described. The page table entry can be used to map a virtual memory address to a physical memory address. In response to a routine accessing the virtual memory address, a permission bit corresponding to the execution domain of the routine and a type of the memory access can be extracted from the page table entry to determine whether the memory access is to be rejected.

A random number generator selects addresses while a ‘scoreboard’ bank of registers (or bits) tracks which addresses have already been output (e.g., for storing or retrieval of a portion of the data.) When the scoreboard detects an address has already been output, a second address which has not been used yet is output rather than the randomly selected one. The second address may be selected from nearby addresses that have not already been output.

A memory device comprises an array of memory cells, a physically unclonable function PUF circuit in the memory device to generate a PUF code, a data path connecting a first circuit to a second circuit in the memory device coupled to the array of memory cells, and logic circuitry to encode data on the data path from the first circuit using the PUF code to produce encoded data, and to provide the encoded data to the second circuit.

A memory includes: a random seed generation circuit suitable for generating a random seed including process variation information; a random signal generator suitable for generating a random signal that is randomly activated based on the random seed; and an address sampling circuit suitable for sampling an active address while the random signal is activated.