A memory device comprises an array of memory cells, a physically unclonable function PUF circuit in the memory device to generate a PUF code, a data path connecting a first circuit to a second circuit in the memory device coupled to the array of memory cells, and logic circuitry to encode data on the data path from the first circuit using the PUF code to produce encoded data, and to provide the encoded data to the second circuit.

A physically unclonable function (PUF) circuit includes a program control transistor, a program select transistor, a read select transistor, and a PUF bit storage transistor. The PUF bit storage transistor has a drain region coupled to the read select transistor, a source region coupled to a source line and the program select transistor, a channel region, a gate dielectric layer, and a gate electrode coupled to the program select transistor. The gate dielectric layer has a first portion formed on the drain region, a second portion formed on the source region, and a main portion formed on the channel region and between the first portion and the second portion, thicknesses of the first portion of the gate dielectric layer and the second portion of the gate dielectric layer being smaller than a thickness of the main portion of the gate dielectric layer.

A physically unclonable function (PUF) circuit includes a program control transistor, a program select transistor, a read select transistor, and a PUF bit storage transistor. The PUF bit storage transistor has a drain region coupled to the read select transistor, a source region coupled to a source line and the program select transistor, a channel region, a gate dielectric layer, and a gate electrode coupled to the program select transistor. The gate dielectric layer has a first portion formed on the drain region, a second portion formed on the source region, and a main portion formed on the channel region and between the first portion and the second portion, thicknesses of the first portion of the gate dielectric layer and the second portion of the gate dielectric layer being smaller than a thickness of the main portion of the gate dielectric layer.

Methods, systems, and devices for spare substitution in a memory system are described. Aspects include a memory device identifying a rotation index that indicates a first assignment of logical channel to physical channels for code words stored in a memory medium. The memory device may use a pointer to indicate one or more code word addresses that are to be rotated and update a value of the pointer associated with a range for the rotation index based on a condition being satisfied. The memory device may rotate a first code word according to a first assignment of the rotation index, where the rotating may occur at an address of the memory medium corresponding to the updated value of the pointer. Additionally, the memory device may execute access operations on the memory medium that include multiplexing multiple logical channels to multiple physical channels based on the rotation index and the pointer.

Embodiments provide a memory device including a memory comprising at least one chip, each chip comprising one or more banks for storing a plurality of bits, each bank comprising a set of rows and columns, each row and column comprising a number of bits, the device further comprising a controller configured to generate access commands to the memory, an access command identifying an address corresponding to a given row of the memory and a command operation to be performed on the given row, wherein the device further comprises a protection device. The protection device is configured to transform an address, in response to the receipt of an access command identifying the address, into a transformed address. The protection device uses an address storage data structure, such as a histogram, to store the transformed address depending on a frequency of access associated with the address, the address storage data structure being reset in response to a memory protection operation (refresh for example) performed in the memory device. The protection device further comprises an access frequency manager configured to determine whether the access frequency associated with an address maintained in the address storage data structure is greater or equal to a threshold, and if so trigger a memory protection operation in the memory from within the memory.

Apparatuses and methods related to row hammer mitigation in, for example, a memory device or a computing system that includes a memory device. Data from a group of memory cells of a memory array can be latched in sensing circuitry responsive to a determination of a hammering event associated with the group of memory cells. Thereafter, the data can be accessed from the sensing circuitry.

Memory devices, systems including memory devices, and methods of operating memory devices are described, in which memory devices are configured to monitor degradations in word line characteristics. The memory device may generate a reference signal in response to an access command directed to a memory array including a plurality of word lines, in some embodiments. The memory array may include a victim word line configured to accumulate adverse effects of executing multiple access commands at the word lines of the memory array. When the degradation in the word line characteristics causes reliability issues (e.g., corrupted data), the memory array is deemed unreliable, and may be blocked from memory operations. The memory device may compare the reference signal and a signal from the victim word line to determine whether preventive measures may be appropriate to avoid (or mitigate) such reliability issues.

Memory devices are disclosed. A memory device may include a source (SRC) plate configured to couple to a number of memory cells. The memory device may also include a resistor coupled between the source plate and a node. Further, the memory device may include at least one transistor coupled between the source plate and the ground voltage, wherein a gate of the at least one transistor is coupled to the node. The transistor may be configured to couple the SRC plate to the ground voltage during a processing stage. The transistor may further be configured to isolate the SRC plate from the ground voltage during an operation stage. Methods and electronic systems are also disclosed.

Memory devices are disclosed. A memory device may include a source (SRC) plate configured to couple to a number of memory cells. The memory device may also include a resistor coupled between the source plate and a node. Further, the memory device may include at least one transistor coupled between the source plate and the ground voltage, wherein a gate of the at least one transistor is coupled to the node. The transistor may be configured to couple the SRC plate to the ground voltage during a processing stage. The transistor may further be configured to isolate the SRC plate from the ground voltage during an operation stage. Methods and electronic systems are also disclosed.

Methods, systems, and devices for spare substitution in a memory system are described. Aspects include a memory device identifying a rotation index that indicates a first assignment of logical channel to physical channels for code words stored in a memory medium. The memory device may use a pointer to indicate one or more code word addresses that are to be rotated and update a value of the pointer associated with a range for the rotation index based on a condition being satisfied. The memory device may rotate a first code word according to a first assignment of the rotation index, where the rotating may occur at an address of the memory medium corresponding to the updated value of the pointer. Additionally, the memory device may execute access operations on the memory medium that include multiplexing multiple logical channels to multiple physical channels based on the rotation index and the pointer.