A semiconductor device including a substrate that has a first region and a second region, a plurality of lower conductive patterns on the substrate, the plurality of lower conductive patterns including a first conductive pattern in the first region of the substrate and a second conductive pattern in the second region of the substrate, a magnetic tunnel junction on the first conductive pattern, a contact between the magnetic tunnel junction and the first conductive pattern, a through electrode on the second conductive pattern, and a plurality of upper conductive patterns on the magnetic tunnel junction and the through electrode. The contact includes a first contact on the lower conductive patterns, a second contact on the first contact, and a first barrier layer that covers a bottom surface and a lateral surface of the second contact.

A semiconductor device including a substrate that has a first region and a second region, a plurality of lower conductive patterns on the substrate, the plurality of lower conductive patterns including a first conductive pattern in the first region of the substrate and a second conductive pattern in the second region of the substrate, a magnetic tunnel junction on the first conductive pattern, a contact between the magnetic tunnel junction and the first conductive pattern, a through electrode on the second conductive pattern, and a plurality of upper conductive patterns on the magnetic tunnel junction and the through electrode. The contact includes a first contact on the lower conductive patterns, a second contact on the first contact, and a first barrier layer that covers a bottom surface and a lateral surface of the second contact.

A magnetic element is provided. The magnetic element includes a free magnetization layer having a surface area that is approximately 1,600 nm2 or less, the free magnetization layer including a magnetization state that is configured to be changed; an insulation layer coupled to the free magnetization layer, the insulation layer including a non-magnetic material; and a magnetization fixing layer coupled to the insulation layer opposite the free magnetization layer, the magnetization fixing layer including a fixed magnetization so as to be capable of serving as a reference of the free magnetization layer.

Some embodiments of the present disclosure relate to a memory device. The memory device includes an active current path including a magnetic tunnel junction (MTJ); and a reference current path including a reference resistance element. The reference resistance element has a resistance that differs from a resistance of the MTJ. An asynchronous, delay-sensing element has a first input coupled to the active current path and a second input coupled to the reference current path. The asynchronous, delay-sensing element is configured to sense a timing delay between a first rising or falling edge voltage on the active current path and a second rising or falling edge voltage on the reference current path. The asynchronous, delay-sensing element is further configured to determine a data state stored in the MTJ based on the timing delay.

A magnetic storage device includes a memory cell with a magnetoresistive effect element and a switching element connected in series. The magnetoresistive effect element is configured to change from a first resistance state to a second resistance state that is lower in resistance than the first resistance state in response to a first write operation flowing current in a first direction through the memory cell and to change from the second resistance state to the first resistance state in response to a second write operation flowing current in a second direction through the memory cell. The switching element has a first voltage drop associated with current flows in the first direction and has a second voltage drop associated with current flows the second direction that is lower than the first voltage drop.

A magnetic storage device includes a memory cell with a magnetoresistive effect element and a switching element connected in series. The magnetoresistive effect element is configured to change from a first resistance state to a second resistance state that is lower in resistance than the first resistance state in response to a first write operation flowing current in a first direction through the memory cell and to change from the second resistance state to the first resistance state in response to a second write operation flowing current in a second direction through the memory cell. The switching element has a first voltage drop associated with current flows in the first direction and has a second voltage drop associated with current flows the second direction that is lower than the first voltage drop.

A semiconductor device is provided. The semiconductor device includes: a processor core which processes program data; a first memory mounted on the same semiconductor chip as the processor core; a second memory including an MRAM cell having a first MTJ (Magnetic Tunnel Junction) structure; a third memory including an MRAM cell having a second MTJ structure different from the first MTJ structure, wherein the processor core selectively stores the program data in one of the first memory, the second memory and the third memory, on the basis of an attribute of the program data.

A magnetic element is provided. The magnetic element includes a free magnetization layer having a surface area that is approximately 1,600 nm2 or less, the free magnetization layer including a magnetization state that is configured to be changed; an insulation layer coupled to the free magnetization layer, the insulation layer including a non-magnetic material; and a magnetization fixing layer coupled to the insulation layer opposite the free magnetization layer, the magnetization fixing layer including a fixed magnetization so as to be capable of serving as a reference of the free magnetization layer.

Some embodiments of the present disclosure relate to a memory device. The memory device includes an active current path including a magnetic tunnel junction (MTJ); and a reference current path including a reference resistance element. The reference resistance element has a resistance that differs from a resistance of the MTJ. An asynchronous, delay-sensing element has a first input coupled to the active current path and a second input coupled to the reference current path. The asynchronous, delay-sensing element is configured to sense a timing delay between a first rising or falling edge voltage on the active current path and a second rising or falling edge voltage on the reference current path. The asynchronous, delay-sensing element is further configured to determine a data state stored in the MTJ based on the timing delay.

Endurance mechanisms are introduced for memories such as non-volatile memories for broad usage including caches, last-level cache(s), embedded memory, embedded cache, scratchpads, main memory, and storage devices. Here, non-volatile memories (NVMs) include magnetic random-access memory (MRAM), resistive RAM (ReRAM), ferroelectric RAM (FeRAM), phase-change memory (PCM), etc. In some cases, features of endurance mechanisms (e.g., randomizing mechanisms) are applicable to volatile memories such as static random-access memory (SRAM), and dynamic random-access memory (DRAM). The endurance mechanisms include a wear leveling scheme that uses index rotation, outlier compensation to handle weak bits, and random swap injection to mitigate wear out attacks.