Endurance mechanisms are introduced for memories such as non-volatile memories for broad usage including caches, last-level cache(s), embedded memory, embedded cache, scratchpads, main memory, and storage devices. Here, non-volatile memories (NVMs) include magnetic random-access memory (MRAM), resistive RAM (ReRAM), ferroelectric RAM (FeRAM), phase-change memory (PCM), etc. In some cases, features of endurance mechanisms (e.g., randomizing mechanisms) are applicable to volatile memories such as static random-access memory (SRAM), and dynamic random-access memory (DRAM). The endurance mechanisms include a wear leveling scheme that uses index rotation, outlier compensation to handle weak bits, and random swap injection to mitigate wear out attacks.

A magnetic storage device includes a memory cell with a magnetoresistive effect element and a switching element connected in series. The magnetoresistive effect element is configured to change from a first resistance state to a second resistance state that is lower in resistance than the first resistance state in response to a first write operation flowing current in a first direction through the memory cell and to change from the second resistance state to the first resistance state in response to a second write operation flowing current in a second direction through the memory cell. The switching element has a first voltage drop associated with current flows in the first direction and has a second voltage drop associated with current flows the second direction that is lower than the first voltage drop.

Embodiments of the present invention disclose an MRAM cell layout for 32 nm, 45 nm, and 65 nm CMOS process technology.

A magnetic element is provided. The magnetic element includes a free magnetization layer having a surface area that is approximately 1,600 nm2 or less, the free magnetization layer including a magnetization state that is configured to be changed; an insulation layer coupled to the free magnetization layer, the insulation layer including a non-magnetic material; and a magnetization fixing layer coupled to the insulation layer opposite the free magnetization layer, the magnetization fixing layer including a fixed magnetization so as to be capable of serving as a reference of the free magnetization layer.

An integrated circuit includes an artificial intelligence (AI) logic and an embedded memory coupled to the AI logic and connectable to an external processor. The embedded memory includes multiple storage cells and multiple reference units. One or more reference units in the memory are selected for memory access through configuration at chip packaging level by the external processor. The external processor may execute a self-test process to select or update the one or more reference units for memory access so that the error rate of memory is below a threshold. The self-test process may be performed, via a memory initialization controller in the memory, to test and reuse the reference cells in the memory at chip level. The embedded memory may be a STT-MRAM, SOT, OST MRAM, and/or MeRAM memory.

An integrated circuit includes an artificial intelligence (AI) logic and an embedded memory coupled to the AI logic and connectable to an external processor. The embedded memory includes multiple storage cells and multiple reference units. One or more reference units in the memory are selected for memory access through configuration at chip packaging level by the external processor. The external processor may execute a self-test process to select or update the one or more reference units for memory access so that the error rate of memory is below a threshold. The self-test process may be performed, via a memory initialization controller in the memory, to test and reuse the reference cells in the memory at chip level. The embedded memory may be a STT-MRAM, SOT, OST MRAM, and/or MeRAM memory.

A magnetic memory includes magnetoresistance effect elements, each of which includes a first ferromagnetic metal layer in which a magnetization direction is fixed, a second ferromagnetic metal layer for a magnetization direction to be changed, and a nonmagnetic layer provided between the first ferromagnetic metal layer and the second ferromagnetic metal layer, a first wiring connected to the first ferromagnetic metal layer of at least one magnetoresistance effect element, spin-orbit torque wirings, each of which is connected to each of the second ferromagnetic metal layers of the magnetoresistance effect elements and extend in a direction intersecting a lamination direction of the magnetoresistance effect element, one first control element connected to the first wiring, one second control element connected to each of first connection points of the spin-orbit torque wirings, and first cell selection elements, each of which is connected to each of second connection points of the spin-orbit torque wirings.

A magnetic element is provided. The magnetic element includes a free magnetization layer having a surface area that is approximately 1,600 nm2 or less, the free magnetization layer including a magnetization state that is configured to be changed; an insulation layer coupled to the free magnetization layer, the insulation layer including a non-magnetic material; and a magnetization fixing layer coupled to the insulation layer opposite the free magnetization layer, the magnetization fixing layer including a fixed magnetization so as to be capable of serving as a reference of the free magnetization layer.

Embodiments of the present invention disclose an MRAM cell layout for 32 nm, 45 nm, and 65 nm CMOS process technology.

A method for fabricating semiconductor device includes the steps of first forming a magnetic tunneling junction (MTJ) stack on a substrate, in which the MTJ stack includes a pinned layer on the substrate, a barrier layer on the pinned layer, and a free layer on the barrier layer. Next, a top electrode is formed on the MTJ stack, the top electrode, the free layer, and the barrier layer are removed, a first cap layer is formed on the top electrode, the free layer, and the barrier layer, and the first cap layer and the pinned layer are removed to form a MTJ and a spacer adjacent to the MTJ.