A memory comprising substrates is provided. Each substrate comprises a through-hole area at center; a first contact area at a side of the through-hole area; and a second contact area at another side of the through-hole area. The substrate uses its first or second contact area to mutually electrically connects to the first or second contact area of the another substrate through the through-hole area. After the pins of the memory having at least PAR pin included are electrically connects to the first and second contact areas of the substrate, all the substrates obtain mutual connections across layers through signal lines with the guidance of the through-hole areas. Thus, on fabricating the memory, reference layer is effectively prevented from breaks with good power distribution and sufficient wiring space achieved while good signal integrity is further maintained.

A memory comprising substrates is provided. Each substrate comprises a through-hole area at center; a first contact area at a side of the through-hole area; and a second contact area at another side of the through-hole area. The substrate uses its first or second contact area to mutually electrically connects to the first or second contact area of the another substrate through the through-hole area. After the pins of the memory having at least PAR pin included are electrically connects to the first and second contact areas of the substrate, all the substrates obtain mutual connections across layers through signal lines with the guidance of the through-hole areas. Thus, on fabricating the memory, reference layer is effectively prevented from breaks with good power distribution and sufficient wiring space achieved while good signal integrity is further maintained.

A semiconductor memory cell including a capacitorless transistor having a floating body configured to store data as charge therein when power is applied to the cell, and a non-volatile memory comprising a bipolar resistive change element, and methods of operating.

A semiconductor memory cell including a capacitorless transistor having a floating body configured to store data as charge therein when power is applied to the cell, and a non-volatile memory comprising a bipolar resistive change element, and methods of operating.

Systems, integrated circuits, and methods to utilize access signals to facilitate memory operations in scaled arrays of memory elements are described. In at least some embodiments, a non-volatile memory device can include a cross-point array having resistive memory elements and line driver. The line driver can be configured to access a resistive memory element in the cross-point array.

Systems, integrated circuits, and methods to utilize access signals to facilitate memory operations in scaled arrays of memory elements are described. In at least some embodiments, a non-volatile memory device can include a cross-point array having resistive memory elements and line driver. The line driver can be configured to access a resistive memory element in the cross-point array.

A semiconductor memory cell including a capacitorless transistor having a floating body configured to store data as charge therein when power is applied to the cell, and a non-volatile memory comprising a bipolar resistive change element, and methods of operating.

A semiconductor memory cell including a capacitorless transistor having a floating body configured to store data as charge therein when power is applied to the cell, and a non-volatile memory comprising a bipolar resistive change element, and methods of operating.

Embodiments of the invention relate generally to semiconductors and memory technology, and more particularly, to systems, integrated circuits, and methods to implement circuits configured to compensate for parameter variations in layers of memory by adjusting access signals during memory operations. In some embodiments, memory cells are based on third dimensional memory technology. In at least some embodiments, an integrated circuit includes multiple layers of memory, a layer including sub-layers of semiconductor material. The integrated circuit also includes an access signal generator configured to generate an access signal to facilitate an access operation, and a characteristic adjuster configured to adjust the access signal for each layer in the multiple layers of memory.

Embodiments of the invention relate generally to semiconductors and memory technology, and more particularly, to systems, integrated circuits, and methods to implement circuits configured to compensate for parameter variations in layers of memory by adjusting access signals during memory operations. In some embodiments, memory cells are based on third dimensional memory technology. In at least some embodiments, an integrated circuit includes multiple layers of memory, a layer including sub-layers of semiconductor material. The integrated circuit also includes an access signal generator configured to generate an access signal to facilitate an access operation, and a characteristic adjuster configured to adjust the access signal for each layer in the multiple layers of memory.