Memory having a controller configured to cause the memory to determine a respective raw data value of a plurality of possible raw data values for each memory cell of a plurality of memory cells, count occurrences of each raw data value for a first set of memory cells of the plurality of memory cells, store a cumulative number of occurrences for each raw data value, determine a plurality of valleys of the stored cumulative number of occurrences for each raw data value with each valley corresponding to a respective raw data value of the plurality of possible raw data values, and, for each memory cell of a second set of memory cells of the plurality of memory cells, determine a data value for that memory cell in response to the raw data value for that memory cell and the respective raw data values of the plurality of valleys.

Various embodiments of the present application are directed towards a method for forming an integrated chip. The method includes forming a dielectric structure over a substrate. A first conductive wire is formed along the dielectric structure. The first conductive wire extends laterally along a first direction. A memory stack is formed on a top surface of the first conductive wire. A second conductive wire is formed over the memory stack. The second conductive wire extends laterally along a second direction orthogonal to the first direction. An upper conductive via is formed on the top surface of the first conductive wire. An upper surface of the upper conductive via is above the second conductive wire.

Various embodiments of the present application are directed towards a method for forming an integrated chip. The method includes forming a dielectric structure over a substrate. A first conductive wire is formed along the dielectric structure. The first conductive wire extends laterally along a first direction. A memory stack is formed on a top surface of the first conductive wire. A second conductive wire is formed over the memory stack. The second conductive wire extends laterally along a second direction orthogonal to the first direction. An upper conductive via is formed on the top surface of the first conductive wire. An upper surface of the upper conductive via is above the second conductive wire.

Apparatus might include an array of memory cells comprising a plurality of strings of series-connected memory cells and a controller for access of the array of memory cells, wherein the controller is configured to cause the apparatus to perform a sense operation on a selected memory cell of a string of series-connected memory cells, and to discharge access lines connected to the string of series-connected memory cells in a defined manner following the sense operation.

When programming an MLC memory device, the disturb characteristics of a program block having multiple memory cells are measured, and the threshold voltage variations of the multiple memory cells are then acquired based on the disturb characteristics of the program block. Next, multiple initial program voltage pulses are provided according to a predetermined signal level, and multiple compensated program voltage pulses are provided by adjusting the multiple initial program voltage pulses. Last, the multiple compensated program voltage pulses are outputted to the program block for programming the multiple memory cells to the predetermined signal level.

When programming and verifying a memory device which includes a plurality of memory cells and a plurality of word lines, a first coarse programming is first performed on a first memory cell among the plurality of memory cells which is controlled by a first word line among the plurality of word lines, and then a second coarse programming is performed on a second memory cell among the plurality of memory cells which is controlled by a second word line among the plurality of word lines. Next, a first coarse verify current is used for determining whether the first memory cell passes a coarse verification and a second coarse verify current is used for determining whether the second memory cell passes a second coarse verification, wherein the second coarse verify current is smaller than the first coarse verify current.

Embodiments provide a scheme for non-parametric PV-level modeling and an optimal read threshold voltage estimation in a memory system. A controller is configured to: generate multiple optimal read threshold voltages corresponding to multiple sets of two cumulative distribution function (CDF) values, respectively; perform read operations on the cells using a plurality of read threshold voltages; generate cumulative mass function (CMF) samples based on the results of the read operations; receive first and second CDF values, selected from among a plurality of CDF values, each CDF value corresponding to each CMF sample; and estimate an optimal read threshold voltage corresponding to the first and second CDF values, among the multiple optimal read threshold voltages.

Embodiments provide a scheme for non-parametric PV-level modeling and an optimal read threshold voltage estimation in a memory system. A controller is configured to: generate multiple optimal read threshold voltages corresponding to multiple sets of two cumulative distribution function (CDF) values, respectively; perform read operations on the cells using a plurality of read threshold voltages; generate cumulative mass function (CMF) samples based on the results of the read operations; receive first and second CDF values, selected from among a plurality of CDF values, each CDF value corresponding to each CMF sample; and estimate an optimal read threshold voltage corresponding to the first and second CDF values, among the multiple optimal read threshold voltages.

A non-volatile memory and a programming method thereof are provided. The programming method of the non-volatile memory includes the following steps. A coarse programming procedure is performed for programing all of a plurality of memory cells at an erase state to 2.sup.∧N-1 or 2.sup.∧N program states. N is a positive integer. A fine programming procedure is performed for pushing all of memory cells into 2.sup.∧N-1 or 2.sup.∧N verify levels.

A 3-dimensional array of NOR memory strings being organized by planes of NOR memory strings, in which (i) the storage transistors in the NOR memory strings situated in a first group of planes are configured to be programmed, erased, program-inhibited or read in parallel, and (ii) the storage transistors in NOR memory strings situated within a second group of planes are configured for storing resource management data relating to data stored in the storage transistors of the NOR memory strings situated within the first group of planes, wherein the storage transistors in NOR memory strings in the second group of planes are configured into sets.