METHOD OF PROGRAMMING MLC MEMORY DEVICE AND RELATED MLC MEMORY DEVICE

Abstract

When programming an MLC memory device, the disturb characteristics of a program block having multiple memory cells are measured, and the threshold voltage variations of the multiple memory cells are then acquired based on the disturb characteristics of the program block. Next, multiple initial program voltage pulses are provided according to a predetermined signal level, and multiple compensated program voltage pulses are provided by adjusting the multiple initial program voltage pulses. Last, the multiple compensated program voltage pulses are outputted to the program block for programming the multiple memory cells to the predetermined signal level.

Claims

1. A method of programing a multi-level cell (MLC) memory device, comprising: measuring a disturb characteristic of a program block in the MLC memory device, wherein the program block includes a plurality of memory cells; acquiring threshold voltage variations of the plurality of memory cells according to the disturb characteristic of the program block; determining a plurality of initial program voltage pulses associated with a predetermined signal level; providing a plurality of compensated program voltage pulses by adjusting the plurality of initial program voltage pulses according to the threshold voltage variations of the plurality of memory cells; and programming the plurality of memory cells to the predetermined signal level by outputting the plurality of compensated program voltage pulses to the program block.

2. The method of claim 1, wherein a control end of each memory cell is coupled to a same word line in the MLC memory device.

3. The method of claim 2, wherein the disturb characteristics of the program block are determined based on a predetermined program distribution of the memory cells coupled to each word line.

4. The method of claim 1, further comprising: providing the plurality of compensated program voltage pulses by adjusting peak values of the plurality of initial program voltage pulses according to the threshold voltage variations of the plurality of memory cells.

5. The method of claim 1, wherein: the plurality of initial program voltage pulses include a 1.sup.st initial program voltage pulse to a P.sup.th initial program voltage pulse; the plurality of compensated program voltage pulses include a 1.sup.st compensated program voltage pulse to a P.sup.th compensated program voltage pulse corresponding to the 1.sup.st initial program voltage pulse to the P.sup.th initial program voltage pulse, respectively; peak values of the 1.sup.st initial program voltage pulse to the P.sup.th initial program voltage pulse increase sequentially; peak values of the 1.sup.st compensated program voltage pulse to the P.sup.th compensated program voltage pulse increase sequentially; and P is an integer larger than 1.

6. The method of claim 5, further comprising: programming the plurality of memory cells to the predetermined signal level by sequentially outputting the 1.sup.st compensated program voltage pulse to the P.sup.th compensated program voltage pulses to the program block.

7. The method of claim 1, further comprising: outputting a plurality of verify voltage pulses to the program block for verifying whether the plurality of memory cells have been programmed to the predetermined signal level.

8. A multi-level cell (MLC) memory device, comprising: a memory array comprising M columns and N rows of memory cells, wherein M and N are integers larger than 1; and a processing circuit configured to: acquire threshold voltage variations of each row of memory cells among the N rows of memory cells according to a disturb characteristic of each row of memory cells; determine a plurality of initial program voltage pulses associated with a predetermined signal level for an operation to program an n.sup.th row of memory cells among the N rows of memory cells to the predetermined signal level, wherein n is a positive integer not larger than N; provide a plurality of compensated program voltage pulses by adjusting the plurality of initial program voltage pulses according to the threshold voltage variation of the n.sup.th row of memory cells; and program the n.sup.th row of memory cells to the predetermined signal level by outputting the plurality of compensated program voltage pulses to the n.sup.th row of memory cells.

9. The MLC memory device of claim 8, wherein the processing circuit is further configured to: provide the plurality of compensated program voltage pulses by adjusting peak values of the plurality of initial program voltage pulses according to the threshold voltage variations of the n.sup.th row of memory cells.

10. The MLC memory device of claim 8, wherein the processing circuit is further configured to: adjust the plurality of compensated program voltage pulses based on a predetermined program distribution of each row of memory cells among the N rows of memory cells.

11. The MLC memory device of claim 8, wherein: the plurality of initial program voltage pulses include a 1.sup.st initial program voltage pulse to a P.sup.th initial program voltage pulse; the plurality of compensated program voltage pulses include a 1.sup.st compensated program voltage pulse to a P.sup.th compensated program voltage pulse corresponding to the 1.sup.st initial program voltage pulse to the P.sup.th initial program voltage pulse, respectively; peak values of the 1.sup.st initial program voltage pulse to the P.sup.th initial program voltage pulse increase sequentially; peak values of the 1.sup.st compensated program voltage pulse to the P.sup.th compensated program voltage pulse increase sequentially; and P is an integer larger than 1.

12. The MLC memory device of claim 8, wherein the processing circuit is further configured to: program the n.sup.th row of memory cells to the predetermined signal level by sequentially outputting the 1.sup.st compensated program voltage pulse to the P.sup.th compensated program voltage pulses to the n.sup.th row of memory cells.

13. The MLC memory device of claim 8, wherein the processing circuit is further configured to: output a plurality of verify voltage pulses to the n.sup.th row of memory cells for verifying whether the n.sup.th row of memory cells have been programmed to the predetermined signal level.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0010] FIG. 1 is a diagram illustrating a prior art method of programing an MLC memory device.

[0011] FIGS. 2A and 2B are diagrams illustrating a prior art ISPP programming method.

[0012] FIG. 3 is a functional block diagram illustrating a memory device according to an embodiment of the present invention.

[0013] FIG. 4 is a flowchart illustrating a method of programing an MLC memory device according to an embodiment of the present invention.

[0014] FIG. 5 is a diagram illustrating the disturb characteristics of the plurality of program blocks and the method of acquiring the threshold voltage variations thereof according to an embodiment of the present invention.

[0015] FIG. 6 is a diagram illustrating the threshold voltage distribution of the memory cells after performing the present program method according to an embodiment of the present invention.

DETAILED DESCRIPTION

[0016] FIG. 3 is a functional block diagram illustrating a memory device 100 according to an embodiment of the present invention. The memory device 100 includes a memory block 110, a row driver 120, a column driver 130, and a processing circuit 140. The memory block 110 includes a plurality of memory cells PX.sub.11-PX.sub.NM arranged in an array, a plurality of word lines WL.sub.1-WL.sub.N, and a plurality of bit lines BL.sub.1-BL.sub.M, wherein M and N are integers larger than 1.

[0017] The processing circuit 140 is configured to control the row driver 120 for outputting row driving signals SG.sub.1-SG.sub.N to the word lines WL.sub.1-WL.sub.N, thereby turning on corresponding rows of memory cells. The processing circuit 140 is configured to control the column driver 130 for outputting column driving signals SC.sub.1-SC.sub.M to the bit lines BL.sub.1-BL.sub.M, thereby performing write, erase and program operations on corresponding memory cells.

[0018] In an embodiment of the present invention, the memory cells PX.sub.11-PX.sub.NM may be non-volatile memory with MLC structure, such as flash memory, random access memory (RAM), programmable read only memory (PROM), or any combination thereof. However, the type of memory cells PX.sub.11-PX.sub.NM does not limit the scope of the present invention.

[0019] FIG. 4 is a flowchart illustrating a method of programing an MLC memory device according to an embodiment of the present invention. The present method includes the following steps:

[0020] Step 410: measure the disturb characteristics of the plurality of program blocks in the memory block 110, wherein each program block includes a plurality of memory cells.

[0021] Step 420: acquire the threshold voltage variations of the plurality of memory cells according to the disturb characteristics of each program block.

[0022] Step 430: determine a plurality of initial program voltage pulses associated with a predetermined signal level.

[0023] Step 440: provide a plurality of compensated program voltage pulses by adjusting the plurality of initial program voltage pulses according to the threshold voltage variations of the plurality of memory cells in a specific program block.

[0024] Step 450: output the plurality of compensated program voltage pulses to the specific program block for programming the corresponding memory cells to the predetermined signal level.

[0025] In step 410, the disturb characteristics of the plurality of program blocks in the memory block 110 are first measured, wherein each program block includes a plurality of memory cells. In step 420, the threshold voltage variations of the plurality of memory cells are then acquired according to the disturb characteristics of each program block. In an embodiment, the memory block 110 includes N program blocks corresponding to the memory cells coupled to the word lines WL.sub.1-WL.sub.N, respectively. In an embodiment, the disturb characteristics of each program block is determined based on the predetermined program distribution of the memory cells coupled to each word line.

[0026] FIG. 5 is a diagram illustrating the disturb characteristics of the plurality of program blocks and the method of acquiring the threshold voltage variations thereof according to an embodiment of the present invention. For illustrative purpose, it is assumed that the memory cells are programmed to eight threshold voltages VT1-VT8 in the present ISPP programming sequence. For example, the row driver 120 is configured to output the row driving signal SG.sub.1 to the word lines WL.sub.1-WL.sub.N for turning on the first row of memory cells PX.sub.11-PX.sub.1N, and the column driver 130 is configured to output the column driving signals SC.sub.1-SC.sub.N to the bit lines BL.sub.1-BL.sub.M sequentially. Assuming that the column driving signals SC.sub.1-SC.sub.N include program voltage pulses having eight different levels similar to those depicted in FIG. 2A and that the first row of memory cells PX.sub.11-PX.sub.1N are programmed to eight threshold voltages VT1-VT8 by the column driving signals SC.sub.1-SC.sub.N, the memory cells programmed to the threshold voltages VT1-VT7 may encounter different degrees of interferences which result in threshold voltage variations ΔVT1-ΔVT7, wherein ΔVT1>ΔVT2> . . . >ΔVT7. Assuming that the column driving signals SC.sub.1-SC.sub.N include program voltage pulses having two different levels similar to those depicted in FIG. 2A and that the second row of memory cells PX.sub.21-PX.sub.2N are programmed to two threshold voltages VT1 and VT8 by the column driving signals SC.sub.1-SC.sub.N, the memory cells programmed to the threshold voltage VT1 may encounter an interference which results in a threshold voltage variation ΔVT1. Assuming that the column driving signals SC.sub.1-SC.sub.N include program voltage pulses having four different levels similar to those depicted in FIG. 2A and that the third row of memory cells PX.sub.31-PX.sub.3N are programmed to four threshold voltages VT1, VT2, VT5 and VT6 by the column driving signals SC.sub.1-SC.sub.N, the memory cells programmed to the threshold voltages VT1, VT2 and VT5 may encounter different degrees of interferences which result in threshold voltage variations ΔVT1, ΔVT2 and ΔVT5, wherein ΔVT1>ΔVT2>ΔVT5.

[0027] In step 430, the plurality of initial program voltage pulses associated with the predetermined signal level may be determined. In step 440, the plurality of compensated voltage pulses may be provided by adjusting the plurality of initial program voltage pulses according to the threshold voltage variations of the plurality of memory cells in the specific program block. The following Table 1 illustrates the method of executing steps 430 and 440 in the present invention. For illustrative purpose, it is also assumed that the memory cells are programmed to eight threshold voltages VT1-VT8 in the present ISPP programming sequence and that the column driving signals SC.sub.1-SC.sub.N include program voltage pulses having eight different levels similar to those depicted in FIG. 2A. The peak values of the program voltage pulses P1′-P8′ are shown in Table. 1, wherein Vpgm represents the initial program voltage value, ΔVt represents the voltage increment, and F(row1)-F(rowN) represent the threshold voltage variations of the memory cells in each program block.

TABLE-US-00001 TABLE 1 First row (WL.sub.1) second row (WL.sub.2) . . . N.sup.th row (WL.sub.N) P1′ Vpgm + F (row1) Vpgm + F(row2) . . . Vpgm + F(rowN) P2′ Vpgm + ΔVt + F (row1) Vpgm + ΔVt + F(row2 ) . . . Vpgm + ΔVt + F(rowN) P3′ Vpgm + 2ΔVt + F(row1) Vpgm + 2ΔVt + F(row2) . . . Vpgm + 2ΔVt + F(rowN) P4′ Vpgm + 3ΔVt + F (row1) Vpgm + 3ΔVt + F(row2) . . . Vpgm + 3ΔVt + F(rowN) P5′ Vpgm + 4ΔVt + F (row1) Vpgm + 4ΔVt + F(row2) . . . Vpgm + 4ΔVt + F(rowN) P6′ Vpgm + 5ΔVt + F (row1) Vpgm + 5ΔVt + F(row2) . . . Vpgm + 5ΔVt + F(rowN) P7′ Vpgm + 6ΔVt + F (row1) Vpgm + 6ΔVt + F(row2) . . . Vpgm + 6ΔVt + F(rowN) P8′ Vpgm + 7ΔVt + F(row1) Vpgm + 7ΔVt + F(row2) . . . Vpgm + 7ΔVt + F(rowN)

[0028] In step 450, the plurality of compensated program voltage pulses are outputted to the specific program block for programming the corresponding memory cells to the predetermined signal level. FIG. 6 is a diagram illustrating the threshold voltage distribution of the memory cells after performing the present program method according to an embodiment of the present invention. For illustrative purpose, it is also assumed that the first row of memory cells PX.sub.11-PX.sub.1N are programmed to eight threshold voltages VT1-VT8 by the column driving signals SC.sub.1-SC.sub.N and that the column driving signals SC.sub.1-SC.sub.N include the compensated program voltage pulses P1′-P8′ having different levels as depicted in Table 1. Since the compensated program voltage pulses adopted in the present program method are associated the threshold voltage variations F(row1)-F(rowN) of the plurality of memory cells, different degrees of interferences encountered by the memory cells may be compensated accordingly. This way, after sequentially applying the compensated program voltage pulses P1′-P8′, the first row of memory cells PX.sub.11-PX.sub.1N may be programmed to the threshold voltages VT1-VT8 accurately.

[0029] In conclusion, the present invention provides a method of programming an MLC memory device and a related MLC memory device. First, a plurality of initial program voltage pulses with increasing voltage levels may be provided using ISPP. Next, a plurality of compensated voltage pulses may be provided by adjusting the plurality of initial program voltage pulses according to the threshold voltage variations of the plurality of memory cells in a specific program block, thereby improving program interferences.

[0030] Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.