Embodiments of an improved memory architecture by processing data inside of the memory device are described. In some embodiments, the memory device can store neural network layers, such as a systolic flow engine, in non-volatile memory and/or a separate DRAM memory. Central processing unit (CPU) of a host system can delegate the execution of a neural network to the memory device. Advantageously, neural network processing in the memory device can be scalable, with the ability to process large amounts of data.

Technologies for blind mating of optical connectors in a rack of a data center are disclosed. In the illustrative embodiment, a sled can be slid into a rack and an optical connector on the sled will blindly mate with a corresponding optical connector on the rack. The illustrative optical connector on the sled includes two guide post receivers which mate with corresponding guide posts on the optical connector on the rack such that, when mated, optical fibers of the optical connector on the rack will be aligned and optically coupled with corresponding optical fibers on the optical connector of the sled.

Technologies for switching network traffic include a network switch. The network switch includes one or more processors and communication circuitry coupled to the one or more processors. The communication circuitry is capable of switching network traffic of multiple link layer protocols. Additionally, the network switch includes one or more memory devices storing instructions that, when executed, cause the network switch to receive, with the communication circuitry through an optical connection, network traffic to be forwarded, and determine a link layer protocol of the received network traffic. The instructions additionally cause the network switch to forward the network traffic as a function of the determined link layer protocol. Other embodiments are also described and claimed.

Technologies for switching network traffic include a network switch. The network switch includes one or more processors and communication circuitry coupled to the one or more processors. The communication circuitry is capable of switching network traffic of multiple link layer protocols. Additionally, the network switch includes one or more memory devices storing instructions that, when executed, cause the network switch to receive, with the communication circuitry through an optical connection, network traffic to be forwarded, and determine a link layer protocol of the received network traffic. The instructions additionally cause the network switch to forward the network traffic as a function of the determined link layer protocol. Other embodiments are also described and claimed.

Technologies for dynamically allocating resources among a set of managed nodes include an orchestrator server to receive telemetry data from the managed nodes indicative of resource utilization and workload performance by the managed nodes as the workloads are executed, generate a resource allocation map indicative of allocations of resources among the managed nodes, determine, as a function of the telemetry data and the resource allocation map, a dynamic adjustment to allocation of resources to at least one of the managed nodes to improve performance of at least one of the workloads executed on the at least one of the managed nodes, and apply the adjustment to the allocation of the resources among the managed nodes as the workloads are executed. Other embodiments are also described and claimed.

To provide a novel semiconductor device.

The semiconductor device includes cell arrays and peripheral circuits; the cell arrays include memory cells; the peripheral circuits includes a first driver circuit, a second driver circuit, a first amplifier circuit, a second amplifier circuit, a third amplifier circuit, and a fourth amplifier circuit; the first driver circuit and the second driver circuit have a function of supplying a selection signal to the cell array; the first amplifier circuit and the second amplifier circuit have a function of amplifying a potential input from the cell array; the third amplifier circuit and the fourth amplifier circuit have a function of amplifying a potential input from the first amplifier circuit or the second amplifier circuit; the first driver circuit, the second driver circuit, the first amplifier circuit, the second amplifier circuit, the third amplifier circuit, and the fourth amplifier circuit include a region overlapping with the cell array; and the memory cells include a metal oxide in a channel formation region.

Examples may include techniques to allocate physical accelerator resources from pools of accelerator resources. In particular, virtual computing devices can be composed from physical resources and physical accelerator resources dynamically allocated to the virtual computing devices. The present disclosure provides that physical accelerator resources can be dynamically allocated, or composed, to a virtual computing device despite not being physically coupled to other components in the virtual device.

Technologies for allocating resources of a set of managed nodes to workloads to manage heat generation include an orchestrator server to receive resource allocation objective data including a target temperature for one or more of the managed nodes. The orchestrator server is also to determine an initial assignment of a set of workloads among the managed nodes, receive telemetry data from the managed nodes indicative of resource utilization by each of the managed nodes and one or more temperatures and fan speeds of the managed nodes as the workloads are performed, predict future heat generation of the workloads as a function of the telemetry data, determine, as a function of the predicted future heat generation, an adjustment to the assignment of the workloads to achieve the target temperature, and apply the adjustments to the assignments of the workloads among the managed nodes as the workloads are performed.

A memory device comprises a first selector and a storage capacitor in series with the first selector. A second selector is in parallel with the storage capacitor coupled between the first selector and zero volts. A plurality of memory devices form a 2S-1C cross-point DRAM array with 4F2 or less density.

A first endpoint comprises a fabric attach point for attachment to a memory fabric, a first media controller, and a first non-volatile memory media. The memory fabric comprises a reliability zone comprising the first endpoint and at least a second endpoint. The first media controller is configured to receive, from at least one processor coupled to the first endpoint via the at least one fabric attach point, a memory fabric store command to store an object in the reliability zone. The first media controller is further configured to store the object in the first non-volatile memory media, to receive from the second endpoint a message indicating that the same object has been stored by the second endpoint, and to send to the at least one processor a single acknowledgement indicating that the at least one object has been stored in both the first and second endpoints of the reliability zone.