A memory calibration method and system and a vehicle system are disclosed. The method includes reading a first set of data from a first memory, wherein the first set of data includes pre-stored parameters for calibrating a second memory comprising a controller; performing a first verification process on the first set of data; performing a second verification process on the first set of data when the first set of data passes the first verification process; adopting the first set of data to configure the controller of the second memory when the first set of data passes the second verification process; and performing a test for the second memory to determine whether finishing a current calibration process for the second memory, wherein the second memory has been calibrated when the second memory passes the test.

Technologies for managing the efficiency of workload execution in a managed node include a managed node that includes one or more processors that each include multiple cores. The managed nodes is to execute threads of workloads assigned to the managed node, generate telemetry data indicative of an efficiency of execution of the threads, determine, as a function of the telemetry data, an adjustment to a configuration of the threads among the cores to increase the efficiency of the execution of the threads, and apply the determined adjustment. Other embodiments are also described and claimed.

A semiconductor device includes a substrate having a volatile memory region and a non-volatile memory region. The volatile memory region includes a cell capacitor disposed in the substrate and a cell transistor connected to the cell capacitor. The non-volatile memory region includes a plurality of non-volatile memory cells disposed on the substrate. The volatile memory region and the non-volatile memory region are disposed side by side.

Embodiments include method, systems and computer program products for operating a dual in-line memory module with dedicated READ and WRITE ports. The computer-implemented method receiving, by a memory controller, one or more memory requests to access a one or more memory modules. The memory controller determines a memory request type for each of the one or more memory requests. The memory controller directs the one or more memory requests to a port of the memory controller dedicated to handle a memory request for an associated memory request type. The memory controller accesses at least a portion of the one or more memory modules via the dedicated port in which the one or more memory requests are directed.

Examples may include racks for a data center and sleds for the racks, the sleds arranged to house physical resources for the data center. The sleds can house physical resources and heat sinks thermally coupled to the physical resources. The physical resources are arranged on the sleds and the heat sinks are configured so as to limit thermal shadowing between physical resources to reduce interference with airflow provided by fans of the racks.

The present disclosure includes methods, and circuits, for operating a memory device. One method embodiment for operating a memory device includes controlling data transfer through a memory interface in an asynchronous mode by writing data to the memory device at least partially in response to a write enable signal on a first interface contact, and reading data from the memory device at least partially in response to a read enable signal on a second interface contact. The method further includes controlling data transfer in a synchronous mode by transferring data at least partially in response to a clock signal on the first interface contact, and providing a bidirectional data strobe signal on an interface contact not utilized in the asynchronous mode.

Technologies for allocating resources of a set of managed nodes to workloads based on resource utilization phase residencies include an orchestrator server to receive resource allocation objective data and determine an assignment of a set of workloads among the managed nodes. The orchestrator server is further to receive telemetry data from the managed nodes, determine, as a function of the telemetry data, phase residency data, determine, as a function of at least the phase residency data and the resource allocation objective data, an adjustment to the assignment of the workloads to increase an achievement of at least one of the resource allocation objectives without decreasing the achievement of any of the other resource allocation objectives, and apply the adjustment to the assignments of the workloads among the managed nodes as the workloads are performed.

Examples may include sleds for a rack in a data center including physical compute resources and memory for the physical compute resources. The memory can be disaggregated, or organized into first level and second level memory. A first sled can comprise the physical compute resources and a first set of physical memory resources while a second sled can comprise a second set of physical memory resources. The first set of physical memory resources can be coupled to the physical compute resources via a local interface while the second set of physical memory resources can be coupled to the physical compute resources via a fabric.

Provided herein are a semiconductor memory device and a method of operating the semiconductor memory device, which have an improved processing speed for a suspend operation. The semiconductor memory device includes a memory cell array, a peripheral circuit configured to perform a data operation corresponding to an externally provided command on the memory cell array and a control circuit configured to control the peripheral circuit to perform the data operation by sequentially executing instructions corresponding to a plurality of instruction lines of an operation algorithm for the data operation and, when a suspend command is provided during the data operation, to perform a preset suspend operation in any one of a checker mode and an instant mode.

A magnetoresistive dynamic random access memory (MDRAM) cell is described. A hybrid memory cell includes a first transistor having a first source/drain electrode coupled to a charge storage node and a gate of a second transistor. A first transistor second source/drain electrode is coupled to a dynamic bit-line, and a gate of the first transistor coupled to a dynamic bit word-line. A resistive memory element is coupled between a select line and the second transistor first source/drain electrode. A third transistor includes a third transistor first source/drain electrode which is coupled to a second source/drain electrode of the second transistor. A third transistor second source/drain electrode is coupled to a nonvolatile bit-line. A gate of the third transistor is coupled to a nonvolatile bit word-line. A memory array of hybrid memory cells and a hybrid memory cell method is also described.