An electronic circuit includes a cell array including memory cells each including a bistable circuit that includes first and second inverter circuits, each having a first mode characterized by there being substantially no hysteresis in transfer characteristics and a second mode characterized by there being hysteresis in the transfer characteristics, and being switchable between the first and second modes, and a control circuit configured to, after powering off a first memory cell that store data that are not required to be retained, put the bistable circuit in a remaining second memory cell into the second mode, and supply a second power supply voltage that allows the bistable circuit in the second mode to retain data and is lower than a first power supply voltage supplied to the bistable circuit when data is read and/or written, to the bistable circuit in the second memory cell while maintaining the second mode.

A novel memory device is provided. The memory device including a plurality of memory cells arranged in a matrix, and each of the memory cells includes a transistor and a capacitor. The transistor includes a first gate and a second gate, which include a region where they overlap with each other with a semiconductor layer therebetween. The memory device has a function of operating in a “writing mode”, a “reading mode”, a “refresh mode”, and an “NV mode”. In the “refresh mode”, data retained in the memory cell is read, and then the read data is written to the memory cell again for first time. In the “NV mode”, data retained in the memory cell is read, the read data is written to the memory cell again for second time, and then a potential at which the transistor is turned off is supplied to the second gate. The “NV mode” operation enables data to be stored for a long time even when power supply to the memory cell is stopped. The memory cell can store multilevel data.

A memory device with reduced power consumption is provided. The memory device includes a plurality of memory cells, a precharge circuit, a latch circuit, a bit line pair, and a local bit line pair. The precharge circuit has a function of supplying precharge voltage to the local bit line pair. The plurality of memory cells are connected to the local bit line pair. The latch circuit is connected to the local bit line pair. The latch circuit in a standby state is preferably supplied with the precharge voltage and one of low power supply voltage and high power supply voltage.

The disclosed technology relates to a non-volatile (NV) static random-access memory (SRAM) device, and to a method of operating the same. The NV-SRAM device includes a plurality of bit-cells, wherein each bit-cell comprises: an SRAM bit-cell; a first bit-line connected via a first access element to the SRAM bit-cell; a NV bit-cell connected via a switch to the SRAM bit-cell; and a second bit-line connected via a second access element to the NV bit-cell. The NV-SRAM device is configured to independently write data from the first bit-line into the SRAM bit-cell through the first access element, and respectively from the second bit-line into the NV bit-cell through the second access element.

One aspect relates to a memory circuit that has a programmable non-volatile memory (NVM) cell configured to generate an NVM output signal indicative of a program state of the NVM cell and to configure a volatile output based on the program state of the NVM cell. The NVM cell comprises a first anti-fuse device, a first select device connected in series with the first anti-fuse device at a first node, and a first pass device. The memory circuit also may have a programmable (independently of the NVM cell) volatile memory (VM) cell configured to receive the NVM output signal at a VM input node and to generate a VM output signal indicative of the program state of the VM cell. The NVM cell may have two NV elements that are separately programmable and are separately selectable via separate access transistors to drive the VM input node.

To reduce the area of a memory cell having a backup function. A storage device includes a cell array, and a row circuit and a column circuit that drive the cell array. The cell array includes a first power supply line, a second power supply line, a word line, a pair of bit lines, a memory cell, and a backup circuit. The cell array is located in a power domain where power gating can be performed. In the power gating sequence of the cell array, data in the memory cell is backed up to the backup circuit. The backup circuit is stacked over a region where the memory cell is formed. A plurality of wiring layers are provided between the backup circuit and the memory cell. The first power supply line, the second power supply line, the word line, and the pair of bit lines are located in different wiring layers.

Power consumption of a semiconductor device is reduced efficiently. The semiconductor device includes a power management unit, a cell array, and a peripheral circuit for driving the cell array. The cell array includes a word line, a bit line pair, a memory cell, and a backup circuit for backing up data in the memory cell. A row circuit and a column circuit are provided in a first power domain capable of power gating, and the cell array is provided in a second power domain capable of power gating. In the operation mode of a memory device, a plurality of low power consumption modes, which have lower power consumption than the standby mode, are set. The power management unit selects one from the plurality of low power consumption modes and performs control for bringing the memory device into the selected low power consumption mode.

A 3D microelectronic device is provided with several superimposed layers of components, with an upper layer including one or several memory cells having a SRAM structure and provided with a rear biasing electrode. The biasing of the rear biasing electrode is modified to switch the memory cells from a ROM operating mode to a SRAM operating mode.

A semiconductor device is provided. The device includes a memory that stores data in a non-volatile and volatile manner and a memory controller configured to control the memory. The memory includes a word line pair including a first and second word line, a first bit line pair orthogonal to the first and the second word line and including a first bit line and a first complementary bit line, and a memory cell pair including first and second memory cells adjacent to the first memory cell in a word line direction. A left node of the first memory cell, and a right node of the first memory cell and a left node of the second memory cell, are all connected to the first word line, and a value of the data stored in the memory cell pair in the non-volatile manner is determined according to the selected first word line.

A semiconductor circuit includes first (IV1, IV3) and second (IV2, IV4) circuits, first (31) and second (32) transistors, a first storage element (35), and a driver (22, 23, 52, 53). The first (IV1, IV3) and second (IV2, IV4) circuits, respectively, apply inverted voltages of voltages at first (N1) and second (N2) nodes to the second (N2) and first (N1) nodes. The first transistor (31) is turned on to couple the first (N1) and third nodes. The second transistor (32) includes a gate coupled to the first node (N1), a drain and a source. One of the drain and the source is coupled to the third node, and another is supplied with a first control voltage (SCL1). The first storage element (35) includes a first end coupled to the third node and a second end supplied with a second control voltage (SCTRL). The first storage element (35) is able to take a first or second resistance state. The driver (22, 23, 52, 53) controls operation of the first transistor (31) and generates the first (SCL1) and second (SCTRL) control voltages.