A novel memory device is provided.

The memory device including a plurality of memory cells arranged in a matrix, and each of the memory cells includes a transistor and a capacitor. The transistor includes a first gate and a second gate, which include a region where they overlap with each other with a semiconductor layer therebetween. The memory device has a function of operating in a writing mode, a reading mode, a refresh mode, and an NV mode. In the refresh mode, data retained in the memory cell is read, and then the read data is written to the memory cell again for first time. In the NV mode, data retained in the memory cell is read, the read data is written to the memory cell again for second time, and then a potential at which the transistor is turned off is supplied to the second gate. The NV mode operation enables data to be stored for a long time even when power supply to the memory cell is stopped. The memory cell can store multilevel data.

A memory storage device is disclosed herein which having volatile memory cells and non-volatile memory cells. The memory storage device can be implemented within a portable electronic device. These portable electronic devices often load data from non-volatile memory cells into volatile memory cells, for example, upon powering up. Conventionally, portable electronic devices often include separate non-volatile memory storage devices and volatile memory storage devices which requires a significant amount of time to transfer data stored in non-volatile memory storage devices to the volatile memory storage devices. However, the memory storage device integrates the volatile memory cells and the non-volatile memory cells into a single integrated memory device. This direct writing of the data stored in the non-volatile memory cells into the volatile memory cells as disclosed herein significantly reduces time required to load data from the non-volatile memory cells to the volatile memory cells which can significantly speed up powering up of portable electronic devices.

A system includes a volatile storage device, a read-only memory (ROM), a memory built-in self-test (BIST) controller and a central processing unit (CPU). The CPU, upon occurrence of a reset event, executes a first instruction from the ROM to cause the CPU to copy a plurality of instructions from a range of addresses in the ROM to the volatile storage device. The CPU also executes a second instruction from the ROM to change a program counter. The CPU further executes the plurality of instructions from the volatile storage device using the program counter. The CPU, when executing the plurality of instructions from the volatile storage device, causes the ROM to enter a test mode and the memory BIST controller to be configured to test the ROM.

To reduce the area of a memory cell having a backup function. A storage device includes a cell array, and a row circuit and a column circuit that drive the cell array. The cell array includes a first power supply line, a second power supply line, a word line, a pair of bit lines, a memory cell, and a backup circuit. The cell array is located in a power domain where power gating can be performed. In the power gating sequence of the cell array, data in the memory cell is backed up to the backup circuit. The backup circuit is stacked over a region where the memory cell is formed. A plurality of wiring layers are provided between the backup circuit and the memory cell. The first power supply line, the second power supply line, the word line, and the pair of bit lines are located in different wiring layers.

A memory device with reduced power consumption is provided.

The memory device includes a plurality of memory cells, a precharge circuit, a latch circuit, a bit line pair, and a local bit line pair. The precharge circuit has a function of supplying precharge voltage to the local bit line pair. The plurality of memory cells are connected to the local bit line pair. The latch circuit is connected to the local bit line pair. The latch circuit in a standby state is preferably supplied with the precharge voltage and one of low power supply voltage and high power supply voltage.

A semiconductor device includes a first wiring having a first portion, a second portion, a third portion provided between the first portion and the second portion, memory cells connected to the third portion of the first wiring, a field effect transistor having a drain connected to the second portion, and a gate, and a second wiring provided in parallel with the first wiring. The third portion of the first wiring includes a fourth portion located nearest to the first portion and a fifth portion located nearest to the second portion. The first wiring further includes a sixth portion disposed between the first portion and the fourth portion. The memory cells include a first memory cell connected to the fourth portion and a second memory cell connected to the fifth portion. The second wiring is electrically connected between the sixth portion and the gate of the field effect transistor.

A system includes a volatile storage device, a read-only memory (ROM), a memory built-in self-test (BIST) controller and a central processing unit (CPU). The CPU, upon occurrence of a reset event, executes a first instruction from the ROM to cause the CPU to copy a plurality of instructions from a range of addresses in the ROM to the volatile storage device. The CPU also executes a second instruction from the ROM to change a program counter. The CPU further executes the plurality of instructions from the volatile storage device using the program counter. The CPU, when executing the plurality of instructions from the volatile storage device, causes the ROM to enter a test mode and the memory BIST controller to be configured to test the ROM.

Disclosed is a semiconductor memory device including a memory cell based on a static random access memory having a 6T or 4T2R configuration and including a first internal node, a second internal node, a first ferroelectric capacitor, and a second ferroelectric capacitor, the first ferroelectric capacitor and the second ferroelectric capacitor having respective first ends connected respectively to the first internal node and the second internal node. For recovering data stored in a non-volatile fashion in the first ferroelectric capacitor and the second ferroelectric capacitor, a first access transistor connected between the first internal node and a first bit line and a second access transistor connected between the second internal node and a second bit line are turned on, and respective capacitive components of the first bit line and the second bit line are used as load capacitances.

A programmable logic device including an asynchronous circuit is provided. The programmable logic device includes a lookup table, a first circuit, and a second circuit. The first circuit receives a first signal and a second signal. The second circuit sends a third signal. The first circuit sends a fourth signal and a fifth signal, when receiving the third signal. The fourth signal has the same logic as the first signal. The fifth signal has the same logic as the second signal. The lookup table sends a sixth signal and a seventh signal, when receiving the fourth signal and the fifth signal. The second circuit sends an eighth signal, when receiving the sixth signal and the seventh signal. The first circuit sends a ninth signal, when receiving the eighth signal. The lookup table includes a memory. The sixth signal and the seventh signal are generated from data stored in the memory.

A non-volatile memory cell includes a floating-gate transistor, a select transistor, and a coupling structure. The floating-gate transistor is deposited in a P-well and includes a gate terminal coupled to a floating gate which is a first polysilicon layer, a drain terminal coupled to a bit line, and a source terminal coupled to a first node. The select transistor is deposited in the P-well and includes a gate terminal coupled to a select gate which is coupled to a word line, a drain terminal coupled to the first node, and a source terminal coupled to the source line. The floating-gate transistor and the select transistor are N-type transistors. The coupling structure is formed by extending the first polysilicon layer to overlap a control gate, in which the control gate is a P-type doped region in an N-well and the control gate is coupled to a control line.