A configuration memory cell includes a latch portion including a cross-coupled latch having complementary output nodes, and a programmable read-only memory (PROM) portion coupled to one of the complementary output nodes of the latch portion, the PROM portion including a programmable and erasable ReRAM device.

A random bit cell includes a random bit cell. The random bit cell includes a volatile memory unit, a first non-volatile memory unit, a second non-volatile memory unit, a first select transistor, and a second select transistor. The first non-volatile memory unit is coupled to a first data terminal of the volatile memory unit, and the second non-volatile memory unit is coupled to a second data terminal of the volatile memory unit. The first select transistor has a first terminal coupled to the first data terminal of the volatile memory unit, a second terminal coupled to a first bit line, and a control terminal coupled to a word line. The second select transistor has a first terminal coupled to the second data terminal of the volatile memory unit, a second terminal coupled to a second bit line, and a control terminal coupled to a word line.

A level shifting circuit generates a pulse signal, when both of the logic levels of two complementary input signals of a level shifter has changed while both of the logic levels of two output signals of the level shifter present at low logic level, to pull up either one of the output signals of the level shifter to a second high logic level. Once the logic level of both output signals at the first output node and the second output node present complementary, the level shifting circuit stops pulling up the output signal.

A nonvolatile memory device includes a memory cell array including a plurality of nonvolatile memory cells; a page buffer circuit connected to the memory cell array through a plurality of bit lines; a calculation circuit configured to perform a calculation on information bits and weight bits based on a calculation window having a first size, the information bits and weight bits being included in a user data set, the memory cell array being configured to store the user data set, the calculation circuit being further configured to receive the user data set through the page buffer circuit; and a data input/output (I/O) circuit connected to the calculation circuit, wherein the calculation circuit is further configured to provide an output data set to the data I/O circuit in response to the calculation circuit completing the calculation with respect to all of the information bits and the weight bits, and wherein the output data set corresponds to a result of the completed calculation.

A system includes a volatile storage device, a read-only memory (ROM), a memory built-in self-test (BIST) controller and a central processing unit (CPU). The CPU, upon occurrence of a reset event, executes a first instruction from the ROM to cause the CPU to copy a plurality of instructions from a range of addresses in the ROM to the volatile storage device. The CPU also executes a second instruction from the ROM to change a program counter. The CPU further executes the plurality of instructions from the volatile storage device using the program counter. The CPU, when executing the plurality of instructions from the volatile storage device, causes the ROM to enter a test mode and the memory BIST controller to be configured to test the ROM.

A memory device with reduced power consumption is provided. The memory device includes a plurality of memory cells, a precharge circuit, a latch circuit, a bit line pair, and a local bit line pair. The precharge circuit has a function of supplying precharge voltage to the local bit line pair. The plurality of memory cells are connected to the local bit line pair. The latch circuit is connected to the local bit line pair. The latch circuit in a standby state is preferably supplied with the precharge voltage and one of low power supply voltage and high power supply voltage.

Provided herein are a semiconductor memory device and a method of operating the semiconductor memory device, which have an improved processing speed for a suspend operation. The semiconductor memory device includes a memory cell array, a peripheral circuit configured to perform a data operation corresponding to an externally provided command on the memory cell array and a control circuit configured to control the peripheral circuit to perform the data operation by sequentially executing instructions corresponding to a plurality of instruction lines of an operation algorithm for the data operation and, when a suspend command is provided during the data operation, to perform a preset suspend operation in any one of a checker mode and an instant mode.

A random bit cell incudes a random bit cell. The random bit cell includes a volatile memory unit, a first non-volatile memory unit, a second non-volatile memory unit, a first select transistor, and a second select transistor. The first non-volatile memory unit is coupled to a first data terminal of the volatile memory unit, and the second non-volatile memory unit is coupled to a second data terminal of the volatile memory unit. The first select transistor has a first terminal coupled to the first data terminal of the volatile memory unit, a second terminal coupled to a first bit line, and a control terminal coupled to a word line. The second select transistor has a first terminal coupled to the second data terminal of the volatile memory unit, a second terminal coupled to a second bit line, and a control terminal coupled to a word line.

A non-volatile memory cell includes a floating-gate transistor, a select transistor, and a coupling structure. The floating-gate transistor is deposited in a P-well and includes a gate terminal coupled to a floating gate which is a first polysilicon layer, a drain terminal coupled to a bit line, and a source terminal coupled to a first node. The select transistor is deposited in the P-well and includes a gate terminal coupled to a select gate which is coupled to a word line, a drain terminal coupled to the first node, and a source terminal coupled to the source line. The floating-gate transistor and the select transistor are N-type transistors. The coupling structure is formed by extending the first polysilicon layer to overlap a control gate, in which the control gate is a P-type doped region in an N-well and the control gate is coupled to a control line.

A level shifting circuit generates a pulse signal, when both of the logic levels of two complementary input signals of a level shifter has changed while both of the logic levels of two output signals of the level shifter present at low logic level, to pull up either one of the output signals of the level shifter to a second high logic level. Once the logic level of both output signals at the first output node and the second output node present complementary, the level shifting circuit stops pulling up the output signal.