The present disclosure provides a memory array. The memory array includes a first memory cell, a first word line, a second word line, a first bit line, a first complementary bit line, a second bit line, a second complementary bit line, a first sense amplifier, a second sense amplifier and a first logic circuit. When the memory array operates in a binary content-addressable memory (BCAM) mode, during a search operation, a first logic output indicates whether a logic level of the first word line matches a first logic value at a first terminal of a first data storage of the first memory cell, and whether a logic level of the second word line matches a first complementary logic value at a second terminal of the first data storage of the first memory cell.

A semiconductor device includes a plurality of memory cells connected to a match line; a word line driver connected to a word line; a valid cell configured to store a valid bit indicating valid or invalid of an entry; a first precharge circuit connected to one end of the match line and configured to precharge the match line to a high level; and a second precharge circuit connected to the other end of the match line and configured to precharge the match line to a high level. The plurality of memory cells are arranged between the first precharge circuit and the second precharge circuit, and the second precharge circuit is arranged between the word line driver and the plurality of memory cells.

A semiconductor device includes a plurality of memory cells connected to a match line; a word line driver connected to a word line; a valid cell configured to store a valid bit indicating valid or invalid of an entry; a first precharge circuit connected to one end of the match line and configured to precharge the match line to a high level; and a second precharge circuit connected to the other end of the match line and configured to precharge the match line to a high level. The plurality of memory cells are arranged between the first precharge circuit and the second precharge circuit, and the second precharge circuit is arranged between the word line driver and the plurality of memory cells.

Systems are methods are provided for implementing an analog content addressable memory (analog CAM), which is particularly structured to allow for an amount of variance (fuzziness) in its search operations. The analog CAM may search for approximate matches with the data stored therein, or matches within a defined variance. Circuitry of the analog CAM may include transistor-source lines that receive search-variance parameters, and/or data lines that receive search-variance parameters explicitly within the search input data. The search-variance parameters may include an upper bound and a lower bound that define a range of values within the allotted amount of fuzziness (e.g., deviation from the stored value). The search-variance parameters may program (using analog approaches) the analog CAM to perform searches having a modifiable restrictiveness that is tuned dynamically, as defined by the input search-variance. Thus, highly efficient hardware for complex applications involving fuzziness are enabled.

Systems are methods are provided for implementing an analog content addressable memory (analog CAM), which is particularly structured to allow for an amount of variance (fuzziness) in its search operations. The analog CAM may search for approximate matches with the data stored therein, or matches within a defined variance. Circuitry of the analog CAM may include transistor-source lines that receive search-variance parameters, and/or data lines that receive search-variance parameters explicitly within the search input data. The search-variance parameters may include an upper bound and a lower bound that define a range of values within the allotted amount of fuzziness (e.g., deviation from the stored value). The search-variance parameters may program (using analog approaches) the analog CAM to perform searches having a modifiable restrictiveness that is tuned dynamically, as defined by the input search-variance. Thus, highly efficient hardware for complex applications involving fuzziness are enabled.

Provided is a memory device for a logic-in-memory. The memory cell includes: a ternary memory cell for storing ternary data: and a weight cell for controlling a current flowing in an operation line on the basis of a weight signal transmitted from the ternary memory cell and an activation signal transmitted via an activation line, wherein the weight cell includes a first transistor for receiving an input of weight data from a first node corresponding to a stored value of the ternary memory cell, a second transistor for receiving an input of inversed weight data from a second node corresponding to an inversed stored value of the ternary memory cell, and a third transistor for receiving an input of an activation signal transmitted via the activation line.

Provided is a memory device for a logic-in-memory. The memory cell includes: a ternary memory cell for storing ternary data: and a weight cell for controlling a current flowing in an operation line on the basis of a weight signal transmitted from the ternary memory cell and an activation signal transmitted via an activation line, wherein the weight cell includes a first transistor for receiving an input of weight data from a first node corresponding to a stored value of the ternary memory cell, a second transistor for receiving an input of inversed weight data from a second node corresponding to an inversed stored value of the ternary memory cell, and a third transistor for receiving an input of an activation signal transmitted via the activation line.

Disclosed is a TCAM device based on a ternary memory cell. A TCAM cell includes a ternary memory cell for storing ternary data and a comparison circuit for obtaining a stored value stored in the ternary memory cell and a search value input via a search line of a search driver, identifying a data match between the stored value and the search value, and outputting a result of the identification via a match line. The comparison circuit includes a first transistor pair that receives an inverted stored value that is an inverted value of the stored value of the ternary memory cell and the search value and a second transistor pair that receives the stored value of the ternary memory cell and an inverted search value that is an inverted value of the search value. The first transistor pair and the second transistor pair are connected in parallel to each other.

Disclosed is a TCAM device based on a ternary memory cell. A TCAM cell includes a ternary memory cell for storing ternary data and a comparison circuit for obtaining a stored value stored in the ternary memory cell and a search value input via a search line of a search driver, identifying a data match between the stored value and the search value, and outputting a result of the identification via a match line. The comparison circuit includes a first transistor pair that receives an inverted stored value that is an inverted value of the stored value of the ternary memory cell and the search value and a second transistor pair that receives the stored value of the ternary memory cell and an inverted search value that is an inverted value of the search value. The first transistor pair and the second transistor pair are connected in parallel to each other.

A substrate housing container (1) includes (i) a container body (10) having one end that is provided with an opening (11) and another end that is provided with a mount element (12) on which substrates (W) are stacked, the mount element 12 facing the opening (11), and (ii) a cover (20) to cover the opening (11), wherein the cover (20) includes a lid portion (21) to cover the opening (11) and at least two holding members (22) disposed on the lid portion (21), the holding members (22) being configured to swing in a central direction of the lid portion (21) and to press outer sides of the substrates (W) accommodated in the container body (10) with the substrates (W) stacked, the container body (10) has guide grooves (13) to make tips (22a) of the holding members (22) move from an outer side of the mount element (12) to an inner sides of the mount element (12) to guide the tips (22a) of the holding members (22) to positions at which the holding members (22) press the outer sides of the substrates (W), and the guide grooves (13) are formed as a dent on surfaces of the mount element (12).