According to one embodiment, there is provided a memory card including a first surface, a second surface, and 1.sup.st to N.sup.th terminal groups. The first surface includes first to N.sup.th rows, where N is an integer of two or greater. The second surface faces the opposite side from the first surface. The 1.sup.st to N.sup.th terminal groups are placed in the first to N.sup.th rows. The 1.sup.st terminal group includes terminals to which differential clock signals are assigned, terminals to which single-ended signals are assigned, and a terminal to which a first power supply voltage is assigned. K.sup.th terminal group, where K is an integer no smaller than two and no greater than N, includes terminals to which differential data signals are assigned.

A 3D semiconductor device including: a first level including a first single-crystal layer, a plurality of first transistors, and at least one metal layer, the metal layer overlaying the first single crystal layer with interconnects between the first transistors forming control circuits; a second level overlaying the metal layer, a plurality of second transistors, and a plurality of first memory cells including at least one of the second transistors; a third level overlaying the second level and including a plurality of third transistors, including second memory cells each including at least one third transistor, where at least one of the second memory cells is at least partially atop of the control circuits, where the control circuits are connected so to control second transistors and third transistors, where the second level is bonded to the third level and to the first level, where the bonded includes oxide to oxide bonds; and a fourth level above the third level, including a second single-crystal layer.

A 3D semiconductor device including: a first level including a first single-crystal layer, a plurality of first transistors, and at least one metal layer, the metal layer overlaying the first single crystal layer with interconnects between the first transistors forming control circuits; a second level overlaying the metal layer, a plurality of second transistors, and a plurality of first memory cells including at least one of the second transistors; a third level overlaying the second level and including a plurality of third transistors, including second memory cells each including at least one third transistor, where at least one of the second memory cells is at least partially atop of the control circuits, where the control circuits are connected so to control second transistors and third transistors, where the second level is bonded to the third level and to the first level, where the bonded includes oxide to oxide bonds; and a fourth level above the third level, including a second single-crystal layer.

A 3D semiconductor device including: a first level including a first single-crystal layer, a plurality of first transistors, and at least one metal layer, the metal layer overlaying the first single crystal layer with interconnects between the first transistors forming control circuits; a second level overlaying the metal layer, a plurality of second transistors, and a plurality of first memory cells including at least one of the second transistors; a third level overlaying the second level and including a plurality of third transistors, including second memory cells each including at least one third transistor, where at least one of the second memory cells is at least partially atop of the control circuits, where the control circuits are connected so to control second transistors and third transistors, where the second level is bonded to the third level and to the first level, where the bonded includes oxide to oxide bonds; and a fourth level above the third level, including a second single-crystal layer.

A 3D semiconductor device including: a first level including a first single-crystal layer, a plurality of first transistors, and at least one metal layer, the metal layer overlaying the first single crystal layer with interconnects between the first transistors forming control circuits; a second level overlaying the metal layer, a plurality of second transistors, and a plurality of first memory cells including at least one of the second transistors; a third level overlaying the second level and including a plurality of third transistors, including second memory cells each including at least one third transistor, where at least one of the second memory cells is at least partially atop of the control circuits, where the control circuits are connected so to control second transistors and third transistors, where the second level is bonded to the third level and to the first level, where the bonded includes oxide to oxide bonds; and a fourth level above the third level, including a second single-crystal layer.

In a semiconductor memory device, voltage application from a memory gate electrode of the memory capacitor to a word line can be blocked by a rectifier element depending on values of voltages applied to the memory gate electrode and the word line without using a conventional control circuit. The configuration eliminates the need to provide a switch transistor and a switch control circuit for turning on and off the switch transistor as in conventional cases, and accordingly achieves downsizing. In the semiconductor memory device, for example, each bit line contact is shared by four anti-fuse memories adjacent to each other and each word line contact is shared by four anti-fuse memories adjacent to each other, thereby achieving downsizing of the entire device as compared to a case in which the bit line contact and the word line contact are individually provided to each anti-fuse memory.

A memory card includes a first surface, a second surface, and 1.sup.st to N.sup.th terminal groups. The first surface includes first to N.sup.th rows, wherein N is an integer of two or greater. The second surface faces the opposite side from the first surface. The 1.sup.st to N.sup.th terminal groups are placed in the first to N.sup.th rows. The 1.sup.st terminal group includes terminals to which differential clock signals are assigned, terminals to which single-ended signals are assigned, and a terminal to which a first power supply voltage is assigned. K.sup.th terminal group, wherein K is an integer no smaller than two and no greater than N, includes terminals to which differential data signals are assigned.

A semiconductor device capable of enlarging a read margin of a memory cell and a method of surrounding a read of a memory are provided. The reference word line RWL is activated in a time division manner with respect to the plurality of word lines WL. The precharge circuit PRE applies the read potential VRD to the bit line BL, and the precharge circuit PRE flows the read current Icel from the selected memory cell MC and the read reference current Iref from the reference cell RC to the bit line BL in a time division manner. A detection currents Ird2a, Irr2a, each of which is a current proportional to the current flowing through the bitline BL, flows through the current detection line CDL.

A semiconductor device capable of enlarging a read margin of a memory cell and a method of surrounding a read of a memory are provided. The reference word line RWL is activated in a time division manner with respect to the plurality of word lines WL. The precharge circuit PRE applies the read potential VRD to the bit line BL, and the precharge circuit PRE flows the read current Icel from the selected memory cell MC and the read reference current Iref from the reference cell RC to the bit line BL in a time division manner. A detection currents Ird2a, Irr2a, each of which is a current proportional to the current flowing through the bitline BL, flows through the current detection line CDL.

A memory device of the non-volatile type including a memory array having a plurality of memory cells organized as sectors, each sector having a main word line associated with a plurality of local word lines, each local word line coupled to the main word line by a respective local word line driver circuit, each of the local word line driver circuits consisting of a first MOS transistor coupled between the respective main word line and a respective local word line and a second MOS transistor coupled between the respective local word line and a first biasing terminal