In a method of forming a one-time-programming (OTP) bit, a thin-film memory device is provided, which includes at least one memory element and a transistor, and the memory element is coupled to the transistor in series. Then, an alternating current is applied to the memory element and the transistor, the power applied to the memory element is constrained, and the transistor is turned on to change the resistance of the memory element for a plurality of cycles of the alternating current until the resistance of the memory element is irreversibly changed.

Various embodiments of the present application are directed towards a one-time-programmable (OTP) implementation using magnetic junctions. In some embodiments, an array comprises multiple magnetic junctions in multiple columns and multiple rows, and the magnetic junctions comprise a first magnetic junction and a second magnetic junction. The first and second magnetic junctions comprise individual top ferromagnetic elements and individual bottom ferromagnetic elements, and further comprise individual barrier elements between the top and bottom ferromagnetic elements. A first barrier element of the first magnetic junction electrically separates first top and bottom ferromagnetic elements of the first magnetic junction. A second barrier element of the second magnetic junction has undergone breakdown, such that it has defects defining a leakage path between second top and bottom ferromagnetic elements of the second magnetic junction. The broken-down state corresponds to a one-time programmed state and is not susceptible to high-temperature change, even at small sizes.

A semiconductor device is provided. The semiconductor device includes: a processor core which processes program data; a first memory mounted on the same semiconductor chip as the processor core; a second memory including an MRAM cell having a first MTJ (Magnetic Tunnel Junction) structure; a third memory including an MRAM cell having a second MTJ structure different from the first MTJ structure, wherein the processor core selectively stores the program data in one of the first memory, the second memory and the third memory, on the basis of an attribute of the program data.

A memory element and methods of constructing the memory element are described. The memory element may include a bottom electrode structure having an uppermost portion of a first dimension. The memory element may further include a MTJ pillar having a bottommost portion forming an interface with the uppermost portion of the bottom electrode structure. The bottommost portion of the MTJ pillar may have a second dimension that is less than the first dimension. The memory element may further include oxidized metal particles located on an outermost sidewall of the MTJ pillar. The memory element may further include a top electrode structure located in the MTJ pillar.

A memory element and methods of constructing the memory element are described. The memory element may include a bottom electrode structure having an uppermost portion of a first dimension. The memory element may further include a MTJ pillar having a bottommost portion forming an interface with the uppermost portion of the bottom electrode structure. The bottommost portion of the MTJ pillar may have a second dimension that is less than the first dimension. The memory element may further include oxidized metal particles located on an outermost sidewall of the MTJ pillar. The memory element may further include a top electrode structure located in the MTJ pillar.

A magnetoresistive random access memory (MRAM) includes an MRAM array having MRAM cells, each including a Magnetic Tunnel Junction (MTJ). The MRAM includes data write circuitry configured to write in one-time-programmable (OTP) write mode or in a non-OTP write mode. In the OTP write mode, the data write circuitry is configured to provide a high write voltage magnitude across selected MRAM cells of a first plurality of MRAM cells so as to permanently blow the corresponding tunnel dielectric layers of the selected MRAM cells. In the non-OTP write mode, the data write circuitry is configured to provide a lower write voltage magnitude across selected MRAM cells so as to set a magnetization of the corresponding free layer of each MRAM cell to modulate a resistance of each MRAM cell, without blowing the corresponding tunnel dielectric layer of each MRAM cell.

A magnetoresistive random access memory (MRAM) includes an MRAM array having MRAM cells, each including a Magnetic Tunnel Junction (MTJ). The MRAM includes data write circuitry configured to write in one-time-programmable (OTP) write mode or in a non-OTP write mode. In the OTP write mode, the data write circuitry is configured to provide a high write voltage magnitude across selected MRAM cells of a first plurality of MRAM cells so as to permanently blow the corresponding tunnel dielectric layers of the selected MRAM cells. In the non-OTP write mode, the data write circuitry is configured to provide a lower write voltage magnitude across selected MRAM cells so as to set a magnetization of the corresponding free layer of each MRAM cell to modulate a resistance of each MRAM cell, without blowing the corresponding tunnel dielectric layer of each MRAM cell.

A semiconductor device is provided. The semiconductor device includes: a processor core which processes program data; a first memory mounted on the same semiconductor chip as the processor core; a second memory including an MRAM cell having a first MTJ (Magnetic Tunnel Junction) structure; a third memory including an MRAM cell having a second MTJ structure different from the first MTJ structure, wherein the processor core selectively stores the program data in one of the first memory, the second memory and the third memory, on the basis of an attribute of the program data.

Various embodiments of the present application are directed towards a one-time-programmable (OTP) implementation using magnetic junctions. In some embodiments, an array comprises multiple magnetic junctions in multiple columns and multiple rows, and the magnetic junctions comprise a first magnetic junction and a second magnetic junction. The first and second magnetic junctions comprise individual top ferromagnetic elements and individual bottom ferromagnetic elements, and further comprise individual barrier elements between the top and bottom ferromagnetic elements. A first barrier element of the first magnetic junction electrically separates first top and bottom ferromagnetic elements of the first magnetic junction. A second barrier element of the second magnetic junction has undergone breakdown, such that it has defects defining a leakage path between second top and bottom ferromagnetic elements of the second magnetic junction. The broken-down state corresponds to a one-time programmed state and is not susceptible to high-temperature change, even at small sizes.

To increase read reliability margins in read-only MRAM arrays, a complimentary pair of MRAM cells includes a first MRAM cell having a first resistance value within a first high resistance range R.sub.H and storing a logic HI value and a second shorted MRAM cell having a second resistance value within a second minimal resistance range R.sub.o and storing a logic LO value. During manufacture and testing, MRAM cells that are assigned logic LO values are permanently shorted prior to distribution such that they permanently exhibit resistance values within the second minimal resistance range R.sub.o. When reading the values stored within the complimentary pair of MRAM cells, a differential sense amplifier applies a common reference current across the first MRAM cell and the second shorted MRAM cell; by shorting cells with logic LO values, a system can reliably read logic values stored within the read-only MRAM array.