A compact three-dimensional mask-programmed read-only memory (3D-MPROM.sub.C) is disclosed. Its memory array and a decoding stage thereof are formed on a same memory level above the substrate. The memory layers of the memory devices in the memory array have at least two different thicknesses, while the middle layer of the decoding device in the decoding stage has the same thickness as the thinnest memory layer.

A compact three-dimensional mask-programmed read-only memory (3D-MPROM.sub.C) is disclosed. Its memory array and a decoding stage thereof are formed on a same memory level above the substrate. The memory layers of the memory devices in the memory array have at least two different thicknesses, while the middle layer of the decoding device in the decoding stage has the same thickness as the thinnest memory layer.

A method for fabricating memory devices includes: forming a gate dielectric layer; forming a first semiconductor film on a first side of the gate dielectric layer; forming a first metal structure on a second side of the gate dielectric layer opposite to the first side, the first metal structure extending along a first lateral direction; forming a first conductive structure on the second side over the first semiconductor film, the first conductive structure extending along the first lateral direction to traverse across the first semiconductor film, and further extending along a vertical direction; forming a second conductive structure on the second side over the first semiconductor film, wherein the second conductive structure extends along the vertical direction; and forming a third conductive structure on the second side over the first semiconductor film, the third conductive structure extending along the vertical direction.

A method for fabricating memory devices includes: forming a gate dielectric layer; forming a first semiconductor film on a first side of the gate dielectric layer; forming a first metal structure on a second side of the gate dielectric layer opposite to the first side, the first metal structure extending along a first lateral direction; forming a first conductive structure on the second side over the first semiconductor film, the first conductive structure extending along the first lateral direction to traverse across the first semiconductor film, and further extending along a vertical direction; forming a second conductive structure on the second side over the first semiconductor film, wherein the second conductive structure extends along the vertical direction; and forming a third conductive structure on the second side over the first semiconductor film, the third conductive structure extending along the vertical direction.

A compact three-dimensional mask-programmed read-only memory (3D-MPROM.sub.c) is disclosed. Its memory array and a decoding stage thereof are formed on a same memory level above the substrate. The memory layers of the memory devices in the memory array have at least two different thicknesses, while the middle layer of the decoding device in the decoding stage has the same thickness as the thinnest memory layer.

A nonvolatile memory cell includes a semiconductor substrate, a first OD region, a second OD region, an isolation region separating the first OD region from the second OD region, a PMOS select transistor disposed on the first OD region, and a PMOS floating gate transistor serially connected to the select transistor and disposed on the first OD region. The PMOS floating gate transistor includes a floating gate overlying the first OD region. A memory P well is disposed in the semiconductor substrate. A memory N well is disposed in the memory P well. The memory P well overlaps with the first OD region and the second OD region. The memory P well has a junction depth that is deeper than a trench depth of the isolation region. The memory N well has a junction depth that is shallower than the trench depth of the isolation region.

A nonvolatile memory cell includes a semiconductor substrate, a first OD region, a second OD region, an isolation region separating the first OD region from the second OD region, a PMOS select transistor disposed on the first OD region, and a PMOS floating gate transistor serially connected to the select transistor and disposed on the first OD region. The PMOS floating gate transistor includes a floating gate overlying the first OD region. A memory P well is disposed in the semiconductor substrate. A memory N well is disposed in the memory P well. The memory P well overlaps with the first OD region and the second OD region. The memory P well has a junction depth that is deeper than a trench depth of the isolation region. The memory N well has a junction depth that is shallower than the trench depth of the isolation region.

A level shift driver circuit comprises a level shift circuit and a driver circuit. The driver circuit comprises a first and a second P-type transistors and a first and a second N-type transistors coupled in series. When a first input signal of the level shift circuit is at an operative voltage, the level shift circuit turns off the second N-type transistor. A control terminal of the first N-type transistor receives the operative voltage to avoid a gate-induced drain leakage current of the second N-type transistor. When the first input signal is at a system base voltage, the level shift circuit turns off the first P-type transistor. A control terminal of the second P-type transistor receives the operative voltage to avoid a gate-induced drain leakage current of the first P-type transistor.

A level shift driver circuit comprises a level shift circuit and a driver circuit. The driver circuit comprises a first and a second P-type transistors and a first and a second N-type transistors coupled in series. When a first input signal of the level shift circuit is at an operative voltage, the level shift circuit turns off the second N-type transistor. A control terminal of the first N-type transistor receives the operative voltage to avoid a gate-induced drain leakage current of the second N-type transistor. When the first input signal is at a system base voltage, the level shift circuit turns off the first P-type transistor. A control terminal of the second P-type transistor receives the operative voltage to avoid a gate-induced drain leakage current of the first P-type transistor.

A memory system includes a memory array comprising a plurality of memory cells. Each of the memory cells includes a transistor coupled to a first capacitor and a second capacitor in series, respectively. The memory system includes an authentication circuit operatively coupled to the memory array. The authentication circuit is configured to generate a Physically Unclonable Function (PUF) signature based on respective logic states of the plurality of memory cells, and wherein the logic state of each of the plurality of memory cells is determined based on a preceding breakdown of either the corresponding first capacitor or second capacitor.