Disclosed are a self-healing memory device including a lower electrode; a polymer nanocomposite layer formed on the lower electrode, wherein, when a structural defect occurs, the polymer nanocomposite layer repairs the structural defect and restores a memory function damaged due to the structural defect through a self-healing mechanism characterized by movement of a polymer material and hydrogen bonding; and an upper electrode formed on the polymer nanocomposite layer and a method of manufacturing the self-healing memory device.

An in-memory digital processor, Perpetual Digital Perceptron (PDP), is disclosed. The digital in-memory processor of the invention processes the input digital information according to a database of the digital content data stored/hardwired in the Content Read Only Memory (CROM) array and outputs the correspondent digital response data stored/hardwired in the Response Read Only Memory (RROM) array. The PDP is the hardwired digital in-memory processor without re-configuration capability and similar to the instinct functions of biological hardwired brains without re-shaping their neuromorphic structures from training and learning.

A memory device is provided. The memory device includes a bit cell having a first invertor connected between a first node and a second node and a second invertor connected between the first node and the second node. The first invertor and the second invertor are cross coupled at a first data node and a second data node. The memory device further includes a pull down circuit connected to the second node. The pull down circuit is operative to pull down a voltage of the second node below a ground voltage in response to an enable signal.

A method for writing to a non-volatile electronic memory with data words and assigned pieces of index information. The non-volatile electronic memory is initially filled exclusively with empty data frames. The empty data frames are overwritable with multi-data frames and/or individual data frames. A multi-data frame includes a selectable number of sequentially stored data words, and a multi-data frame header. A frame-type marker, the number of data words, and a selectable start index are stored in the multi-data frame header so that each data word is assignable a unique index value from an index interval by incrementing or decrementing. An individual data frame includes one data word and an individual data frame header. A frame-type marker and a selectable index value for the one data word of the individual data frame are stored in the individual data frame header.

A timing of an execution of a command in a memory device can be affected delay elements. The delay elements of a unit of delay elements can cause variable delays of the command paths. The delay elements can be activated based on settings stored in a fuse array of a memory device. The delay elements can be used to change a timing of current draw of the memory devices.

A memory device is provided. The memory device includes a bit cell having a first invertor connected between a first node and a second node and a second invertor connected between the first node and the second node. The first invertor and the second invertor are cross coupled at a first data node and a second data node. The memory device further includes a pull down circuit connected to the second node. The pull down circuit is operative to pull down a voltage of the second node below a ground voltage in response to an enable signal.

An OTP (One-Time Programmable) memory cell in an array has a programming MOSFET and symmetrically placed access transistors on either side of the programming MOSFET. The balanced layout of the memory cell improves photolithographic effects with a resulting improved process results. Results of programming the memory cell is also improved.

The present disclosure relates to method and system of implementing one wire programmable circuit by using the same terminal OUT as both main circuit output terminal and the digital I/O interfacing terminal of the circuit. The present invention overcomes the shortcoming of prior arts and does not require the circuit to be powered down first and then powered up again each time the circuit is switched between interfacing mode (read/write/program OTP) and the normal output mode, therefore shorten the time of interfacing with the OTP as well as simplified the interfacing system used to read/write/program the OTP. The present invention also enables the possibility to put the no longer required system clock into sleeping mode after the OTP has been programmed, and has the advantages of reducing system power consumption as well as system noise due to the existing of digital clock.

Embodiments disclosed herein describe a multi-dimensional code storage and transfer system. The system gets electrical power from the flash light of a typical smart device, and displays a time-varying multi-dimensional code which can be captured and decoded by the smart device. The system can be made by printed electronics technology.

A semiconductor system according to an embodiment includes: a semiconductor system including a normal memory cell array and a redundancy memory cell array for repairing a defective cell among memory cells within the normal memory cell array, and configured to output to an external a fail flag generated according to a number of fail bits within read data output from the redundancy memory cell array; and a host configured to store an address corresponding to the read data into a selected register group from among a plurality of register groups, the selected register group being matched to the fail flag.