According to one embodiment, a shift register memory writes data having a first size corresponding to a capacity of a block to a plurality of layers of a plurality of data storing shift strings included in the block, in response to a first command sequence specifying a first write mode from a controller. In response to a second command sequence specifying a second write mode from the controller, the shift register memory writes data having a second size smaller than the capacity of the block to the plurality of layers of one or more first data storing shift strings of the plurality of data storing shift strings, without writing data to each of other data storing shift strings except the one or more first data storing shift strings.

A level shifter including a transistor that can be formed through the same process as a display portion is provided. A semiconductor device serves as a level shifter including transistors having the same conductivity type. The semiconductor device includes a so-called MIS capacitor in which metal, an insulator, and a semiconductor are stacked as a capacitor for boosting an input signal. Since the MIS capacitor is used, the gate-source voltage of a transistor for generating an output signal can be increased. Thus, boosting operation to generate the output signal can be performed more surely.

A level shifter including a transistor that can be formed through the same process as a display portion is provided. A semiconductor device serves as a level shifter including transistors having the same conductivity type. The semiconductor device includes a so-called MIS capacitor in which metal, an insulator, and a semiconductor are stacked as a capacitor for boosting an input signal. Since the MIS capacitor is used, the gate-source voltage of a transistor for generating an output signal can be increased. Thus, boosting operation to generate the output signal can be performed more surely.

According to one embodiment, a shift register memory writes data having a first size corresponding to a capacity of a block to a plurality of layers of a plurality of data storing shift strings included in the block, in response to a first command sequence specifying a first write mode from a controller. In response to a second command sequence specifying a second write mode from the controller, the shift register memory writes data having a second size smaller than the capacity of the block to the plurality of layers of one or more first data storing shift strings of the plurality of data storing shift strings, without writing data to each of other data storing shift strings except the one or more first data storing shift strings.

A signal channel includes at least one first signal line positioned in a first signal layer and at least one second signal line positioned in a second signal layer. The first signal layer extends in a first horizontal direction. The second signal layer extends along a second horizontal plane parallel to the first horizontal plane and spaced apart from the first horizontal plane along a vertical direction orthogonal to the first and second horizontal planes. The first signal line includes a first coupling segment and the second signal line includes a second coupling segment. The first coupling segment at least partially overlaps the second coupling segment along the vertical direction. The first and second coupling segments are positioned to form a greater degree of capacitive coupling between the first and second coupling segments than a degree of capacitive coupling formed between other segments of the first and second signal lines.

A signal channel includes at least one first signal line positioned in a first signal layer and at least one second signal line positioned in a second signal layer. The first signal layer extends in a first horizontal direction. The second signal layer extends along a second horizontal plane parallel to the first horizontal plane and spaced apart from the first horizontal plane along a vertical direction orthogonal to the first and second horizontal planes. The first signal line includes a first coupling segment and the second signal line includes a second coupling segment. The first coupling segment at least partially overlaps the second coupling segment along the vertical direction. The first and second coupling segments are positioned to form a greater degree of capacitive coupling between the first and second coupling segments than a degree of capacitive coupling formed between other segments of the first and second signal lines.

A magnetic wall utilization spin MOSFET includes a magnetic wall driving layer including a magnetic wall, a first region, a second region, and a third region located between the first region and the second region, a channel layer, a magnetization free layer provided at a first end portion of a first surface of the channel layer, and arranged so as to be in contact with the third region of the magnetic wall driving layer, a magnetization fixed layer provided at a second end portion opposite to the first end portion, and a gate electrode provided between the first end portion and the second end portion of the channel layer through a gate insulating layer.

A magnetic wall utilization spin MOSFET includes a magnetic wall driving layer including a magnetic wall, a first region, a second region, and a third region located between the first region and the second region, a channel layer, a magnetization free layer provided at a first end portion of a first surface of the channel layer, and arranged so as to be in contact with the third region of the magnetic wall driving layer, a magnetization fixed layer provided at a second end portion opposite to the first end portion, and a gate electrode provided between the first end portion and the second end portion of the channel layer through a gate insulating layer.

A magnetic wall utilization spin MOSFET includes a magnetic wall driving layer including a magnetic wall, a first region, a second region, and a third region located between the first region and the second region, a channel layer, a magnetization free layer provided at a first end portion of a first surface of the channel layer, and arranged so as to be in contact with the third region of the magnetic wall driving layer, a magnetization fixed layer provided at a second end portion opposite to the first end portion, and a gate electrode provided between the first end portion and the second end portion of the channel layer through a gate insulating layer.

A magnetic wall utilization spin MOSFET includes a magnetic wall driving layer including a magnetic wall, a first region, a second region, and a third region located between the first region and the second region, a channel layer, a magnetization free layer provided at a first end portion of a first surface of the channel layer, and arranged so as to be in contact with the third region of the magnetic wall driving layer, a magnetization fixed layer provided at a second end portion opposite to the first end portion, and a gate electrode provided between the first end portion and the second end portion of the channel layer through a gate insulating layer.