A marching memory is disclosed having an array of memory units. Each memory unit has a sequence of bit level cells. Each bit-level cell has a transfer-transistor having a first main-electrode connected to a clock signal supply line through a first delay element, and a control-electrode connected to an output terminal of a first neighboring bit-level cell positioned at an input side of the array of the memory units, through a second delay element. Each bit-level cell also has a reset-transistor having a first main-electrode connected to a second main-electrode of the transfer-transistor, a control-electrode connected to the clock signal supply line, and a second main-electrode connected to the ground potential. Each bit-level cell also has a capacitor connected in parallel with the reset-transistor.

In a semiconductor device and a shift register, low noise is caused in a non-selection period and a transistor is not always on. First to fourth transistors are provided. One of a source and a drain of the first transistor is connected to a first wire, the other of the source and the drain thereof is connected to a gate electrode of the second transistor, and a gate electrode thereof is connected to a fifth wire. One of a source and a drain of the second transistor is connected to a third wire and the other of the source and the drain thereof is connected to a sixth wire.

A capacitor comprises a first electrode, a second electrode provided on the first electrode, a ferroelectric film provided between the first electrode and the second electrode, and a dielectric film provided between the ferroelectric film and the second electrode, impedance of the ferroelectric film and impedance of the dielectric film are determined such that a control voltage applied between the first electrode and the second electrode is equal to a capacitance boosting operating voltage, and the capacitance boosting operating voltage is determined by the following equation:

[00001]$V_{\mathrm{MAX}}=\left(1+\frac{.Math.Z_2.Math.}{.Math.Z_1.Math.}\right)t_F{E}_{\mathrm{FM}}$

where V.sub.MAX is a capacitance boosting operating voltage, Z.sub.1 is impedance of the ferroelectric film, Z.sub.2 is impedance of the dielectric film, t.sub.F is a thickness of the ferroelectric film, and E.sub.FM is an electric field applied to the ferroelectric film having a maximum polarization.

A capacitor comprises a first electrode, a second electrode provided on the first electrode, a ferroelectric film provided between the first electrode and the second electrode, and a dielectric film provided between the ferroelectric film and the second electrode, impedance of the ferroelectric film and impedance of the dielectric film are determined such that a control voltage applied between the first electrode and the second electrode is equal to a capacitance boosting operating voltage, and the capacitance boosting operating voltage is determined by the following equation:

[00001]$V_{\mathrm{MAX}}=\left(1+\frac{.Math.Z_2.Math.}{.Math.Z_1.Math.}\right)t_F{E}_{\mathrm{FM}}$

where V.sub.MAX is a capacitance boosting operating voltage, Z.sub.1 is impedance of the ferroelectric film, Z.sub.2 is impedance of the dielectric film, t.sub.F is a thickness of the ferroelectric film, and E.sub.FM is an electric field applied to the ferroelectric film having a maximum polarization.

It is an object to provide a semiconductor device which can supply a signal with sufficient amplitude to a scan line while power consumption is kept small. Further, it is an object to provide a semiconductor device which can suppress distortion of a signal supplied to the scan line and shorten a rising time and a falling time while power consumption is kept small. A semiconductor device which includes a plurality of pixels each including a display element and at least one first transistor and a scan line driver circuit supplying a signal for selecting the plurality of pixels to a scan line. A light-transmitting conductive layer is used for a pixel electrode layer of the display element, a gate electrode layer of the first transistor, source and drain electrode layers of the first transistor, and the scan line. The scan line driver circuit includes a second transistor and a capacitor for holding a voltage between a gate electrode layer of the second transistor and a source electrode layer of the second transistor. The source electrode of the second transistor is connected to the scan line.

A semiconductor device in which a decrease in the yield by electrostatic destruction can be prevented is provided. A scan line driver circuit for supplying a signal for selecting a plurality of pixels to a scan line includes a shift register for generating the signal. One conductive film functioning as respective gate electrodes of a plurality of transistors in the shift register is divided into a plurality of conductive films. The divided conductive films are electrically connected to each other by a conductive film which is formed in a layer different from the divided conductive films are formed. The plurality of transistors includes a transistor on an output side of the shift register.

To reduce a leakage current of a transistor so that malfunction of a logic circuit can be suppressed. The logic circuit includes a transistor which includes an oxide semiconductor layer having a function of a channel formation layer and in which an off current is 1×10.sup.−13 A or less per micrometer in channel width. A first signal, a second signal, and a third signal that is a clock signal are input as input signals. A fourth signal and a fifth signal whose voltage states are set in accordance with the first to third signals which have been input are output as output signals.

A display panel, a stage circuit, and a driving method of the stage circuit are provided. The stage circuit includes cascaded shift register circuits. Each cascaded shift register circuit includes: a first control module, a second control module, and an output module. The first control module receives an input signal and a charging signal, and generates a voltage signal at a second node in response to a first clock signal and a voltage signal at a first node. With an exception of a first stage cascaded shift register circuit, a first transistor of a current stage cascaded shift register circuit has a first end connected to a signal output terminal of a previous stage cascaded shift register circuit, a second end connected to the second node, and a control end connected to the first node.

A shift register and driving method thereof, a gate driving circuit and a display device are provided. The shift register includes a first input unit, a second input unit, a pull-up control unit, a pull-down control unit, an output control unit and an output reset unit, wherein the first input unit, the second input unit, the pull-up control unit, the pull-down control unit and the output control unit are coupled to a first node, and the pull-up control unit, the pull-down control unit and the output reset unit are coupled to a second node.

A computer system and method for sequencing deoxyribonucleic acid (DNA), to determine the order of the different nucleotides in a genomic sequence or sequence fragment. An alignment system employs a direct “brute force” Hamming distance calculation between a read sequence and a reference genome. The alignment system is configured to compare directly a set of DNA fragments to a reference genome in a short period, and with the higher probability of accuracy than similar comparison systems given the same number of clock cycles. Each DNA fragment is compared with a reference genome for the entire length of the latter using arrangements of memory cells for storing read sequences and inverse complements of the read sequences, shift registers for streaming the reference genome, and circuitry for calculating and summing the distance between the reference, the read sequence, and the inverse complement in parallel. Both digital and analog implementations are described.