Systems formed by a multi-bit three-transistor (3T) memory cell (i.e., dynamic-analog RAM) are provided. The 3T memory cell includes: a read-access transistor M.sub.1 in electrical communication with a read bitline; a switch transistor M.sub.2 in electrical communication with the read-access transistor M.sub.1 a write-access transistor M.sub.3 in electrical communication with the read-access transistor M.sub.1 and a write bitline; and a memory node MEM in electrical communication between the read-access transistor M.sub.1 and the write-access transistor M.sub.3, wherein the memory node MEM is configured to store a 4-bit weight WE. An array of the 3T memory cells (i.e., dynamic-analog RAMs) may form a computing-in-memory (CIM) macro, and further form a convolutional neural network (CNN) accelerator by communicating with an application-specific integrated circuit (ASIC) which communicates with a global weight static random access memory and an activation static random access memory.

Systems formed by a multi-bit three-transistor (3T) memory cell (i.e., dynamic-analog RAM) are provided. The 3T memory cell includes: a read-access transistor M.sub.1 in electrical communication with a read bitline; a switch transistor M.sub.2 in electrical communication with the read-access transistor M.sub.1 a write-access transistor M.sub.3 in electrical communication with the read-access transistor M.sub.1 and a write bitline; and a memory node MEM in electrical communication between the read-access transistor M.sub.1 and the write-access transistor M.sub.3, wherein the memory node MEM is configured to store a 4-bit weight WE. An array of the 3T memory cells (i.e., dynamic-analog RAMs) may form a computing-in-memory (CIM) macro, and further form a convolutional neural network (CNN) accelerator by communicating with an application-specific integrated circuit (ASIC) which communicates with a global weight static random access memory and an activation static random access memory.

A semiconductor device with a small circuit area that consumes low power is provided. The semiconductor device includes a shift register, a sample-and-hold circuit, a first buffer circuit, and a second buffer circuit. The sample-and-hold circuit includes a first input terminal, a second input terminal, and an output terminal. An output terminal of the first buffer circuit is electrically connected to the first input terminal. The shift register is electrically connected to the second input terminal. An input terminal of the second buffer circuit is electrically connected to the output terminal of the sample-and-hold circuit. In the semiconductor device, the potential of an input analog signal is retained in the sample-and-hold circuit and the analog signal is output from an output terminal of the second buffer circuit.

A semiconductor device with a small circuit area that consumes low power is provided. The semiconductor device includes a shift register, a sample-and-hold circuit, a first buffer circuit, and a second buffer circuit. The sample-and-hold circuit includes a first input terminal, a second input terminal, and an output terminal. An output terminal of the first buffer circuit is electrically connected to the first input terminal. The shift register is electrically connected to the second input terminal. An input terminal of the second buffer circuit is electrically connected to the output terminal of the sample-and-hold circuit. In the semiconductor device, the potential of an input analog signal is retained in the sample-and-hold circuit and the analog signal is output from an output terminal of the second buffer circuit.

The present disclosure provides a shift register unit whose operating time includes a plurality of multi-frame periods, each of the multi-frame periods including a plurality of frame periods. The shift register unit includes a trigger signal input terminal, an input module, a pull-up module, a pull-down control module, a plurality of pull-down modules, and a signal output terminal. The pull-down control module is configured to sequentially provide active signals to the control terminals of respective pull-down modules in pull-down stages of respective frame periods of one multi-frame period. The present disclosure further provides a shift register, a gate driving circuit and a display panel. The shift register unit has longer lifetime and better electric performance, and can meet the requirements of high-reliability products.

The present disclosure provides a shift register unit whose operating time includes a plurality of multi-frame periods, each of the multi-frame periods including a plurality of frame periods. The shift register unit includes a trigger signal input terminal, an input module, a pull-up module, a pull-down control module, a plurality of pull-down modules, and a signal output terminal. The pull-down control module is configured to sequentially provide active signals to the control terminals of respective pull-down modules in pull-down stages of respective frame periods of one multi-frame period. The present disclosure further provides a shift register, a gate driving circuit and a display panel. The shift register unit has longer lifetime and better electric performance, and can meet the requirements of high-reliability products.

Provided is a track-and-hold circuit capable of reducing the power consumption of a differential amplifier circuit while preserving the broadband nature (without narrowing the bandwidth). In the track-and-hold circuit 1 including a differential amplifier circuit 10, a switch circuit 20, and a hold capacitor C.sub.21, the differential amplifier circuit 10 includes a first resistor R.sub.11 having one end connected to a collector electrode of a first transistor Q.sub.11 constituting a differential pair, a second resistor R.sub.12 having one end connected to the collector electrode of a second transistor Q.sub.12 constituting the differential pair, and a third resistor R.sub.13 to which the other end of the first resistor R.sub.11 and the other end of the second resistor R.sub.12 are connected and which is connected between the other ends and a power supply V.sub.CC.

In described examples, a storage cell ring includes circularly coupled storage cells. Each storage cell includes a respective capacitor for generating a respective integrated voltage responsive to a respective duration a respective storage cell is selected, a respective thresholding converter for generating a respective thresholded signal for indicating whether the respective integrated voltage has crossed a threshold, and respective selection circuitry configured to generate a respective select signal responsive to select signals generated by a respective adjacent storage cells. The ring is coupled to an analog quantifier for generating a conversion value responsive to the generated respective integrated voltage and a respective select signal. The ring is coupled to a loop counter for generating a loop count value responsive to changes of values of at least some of the respective thresholded signals. The conversion value and the loop count value can comprise a time measurement.

A semiconductor device with a small circuit area that consumes low power is provided. The semiconductor device includes a shift register, a sample-and-hold circuit, a first buffer circuit, and a second buffer circuit. The sample-and-hold circuit includes a first input terminal, a second input terminal, and an output terminal. An output terminal of the first buffer circuit is electrically connected to the first input terminal. The shift register is electrically connected to the second input terminal. An input terminal of the second buffer circuit is electrically connected to the output terminal of the sample-and-hold circuit. In the semiconductor device, the potential of an input analog signal is retained in the sample-and-hold circuit and the analog signal is output from an output terminal of the second buffer circuit.

A semiconductor device with a small circuit area that consumes low power is provided. The semiconductor device includes a shift register, a sample-and-hold circuit, a first buffer circuit, and a second buffer circuit. The sample-and-hold circuit includes a first input terminal, a second input terminal, and an output terminal. An output terminal of the first buffer circuit is electrically connected to the first input terminal. The shift register is electrically connected to the second input terminal. An input terminal of the second buffer circuit is electrically connected to the output terminal of the sample-and-hold circuit. In the semiconductor device, the potential of an input analog signal is retained in the sample-and-hold circuit and the analog signal is output from an output terminal of the second buffer circuit.