An organic light-emitting display panel, driving method thereof, and an organic light-emitting display device are provided. The organic light-emitting display panel comprises a plurality of pixel driving circuits including a first, a second and a third pixel driving circuits along a row direction. The first and the second pixel driving circuits share a same reference voltage signal line. The second and the third pixel driving circuits share a same data voltage signal line. A plurality of reference voltage signal lines is connected to the plurality of pixel driving circuits. A plurality of data voltage signal lines is connected to the plurality of pixel driving circuits. A first control signal line is connected to the first and third pixel driving circuits. A second control signal line is connected to the second pixel driving circuit. A light-emitting control signal line is connected to the first, second, and third pixel driving circuits.

A gate driving circuit sequentially outputting a gate voltage using a high level power voltage, a low level power voltage, a start voltage, a previous stage gate voltage, a next stage gate voltage and a clock, includes: a shift register including a plurality of stages connected to each other by a cascade connection, each of the plurality of stages including: a first thin film transistor (TFT) switched by the start voltage or the previous stage gate voltage and transmitting the high level power voltage to a Q node; a second TFT switched by the next stage gate voltage and transmitting the low level power voltage to the Q node; a third TFT switched by a voltage of the Q node and transmitting the clock to an output node; and a first resistor connected between the output node and the low level power voltage.

A flexible display panel and a driving method thereof, and a display device are provided. The flexible display panel includes a pixel region and a gate driving circuit region located outside the pixel region. The flexible display panel further includes a curvature adjusting unit located on two sides of the pixel region, the curvature adjusting unit includes a plurality of isosceles trapezoid units which are sequentially connected with each other through lower surfaces thereof, each isosceles trapezoid unit includes an upper surface, the lower surface, and a third waist surface and a fourth waist surface oppositely arranged between the upper surface and the lower surface, and a length of the upper surface between the third waist surface and the fourth waist surface is less than a length of the lower surface between the third waist surface and the fourth waist surface. In the case that the display panel is bent and in a bent portion of the display panel, the third waist surface of the isosceles trapezoid unit attaches to the fourth waist surface of the isosceles trapezoid unit adjacent thereto, and the upper surface of the isosceles trapezoid unit is connected with the upper surface of the isosceles trapezoid unit adjacent thereto.

A flexible display panel and a driving method thereof, and a display device are provided. The flexible display panel includes a pixel region and a gate driving circuit region located outside the pixel region. The flexible display panel further includes a curvature adjusting unit located on two sides of the pixel region, the curvature adjusting unit includes a plurality of isosceles trapezoid units which are sequentially connected with each other through lower surfaces thereof, each isosceles trapezoid unit includes an upper surface, the lower surface, and a third waist surface and a fourth waist surface oppositely arranged between the upper surface and the lower surface, and a length of the upper surface between the third waist surface and the fourth waist surface is less than a length of the lower surface between the third waist surface and the fourth waist surface. In the case that the display panel is bent and in a bent portion of the display panel, the third waist surface of the isosceles trapezoid unit attaches to the fourth waist surface of the isosceles trapezoid unit adjacent thereto, and the upper surface of the isosceles trapezoid unit is connected with the upper surface of the isosceles trapezoid unit adjacent thereto.

A semiconductor device with a small circuit area that consumes low power is provided. The semiconductor device includes a shift register, a sample-and-hold circuit, a first buffer circuit, and a second buffer circuit. The sample-and-hold circuit includes a first input terminal, a second input terminal, and an output terminal. An output terminal of the first buffer circuit is electrically connected to the first input terminal. The shift register is electrically connected to the second input terminal. An input terminal of the second buffer circuit is electrically connected to the output terminal of the sample-and-hold circuit. In the semiconductor device, the potential of an input analog signal is retained in the sample-and-hold circuit and the analog signal is output from an output terminal of the second buffer circuit.

A semiconductor device with a small circuit area that consumes low power is provided. The semiconductor device includes a shift register, a sample-and-hold circuit, a first buffer circuit, and a second buffer circuit. The sample-and-hold circuit includes a first input terminal, a second input terminal, and an output terminal. An output terminal of the first buffer circuit is electrically connected to the first input terminal. The shift register is electrically connected to the second input terminal. An input terminal of the second buffer circuit is electrically connected to the output terminal of the sample-and-hold circuit. In the semiconductor device, the potential of an input analog signal is retained in the sample-and-hold circuit and the analog signal is output from an output terminal of the second buffer circuit.

The circuit includes a first transistor; a second transistor whose first terminal is connected to a gate of the first transistor for setting the potential of the gate of the first transistor to a level at which the first transistor is turned on; a third transistor for setting the potential of a gate of the second transistor to a level at which the second transistor is turned on and bringing the gate of the second transistor into a floating state; and a fourth transistor for setting the potential of the gate of the second transistor to a level at which the second transistor is turned off. With such a configuration, a potential difference between the gate and a source of the second transistor can be kept at a level higher than the threshold voltage of the second transistor, so that operation speed can be improved.

Provided are an array substrate, a display panel and a display device, and the array substrate includes: at least one pressure sensor disposed in the non-display region; and the pressure sensor includes a first resistor, a second resistor, a third resistor and a fourth resistor; and a plurality of shift registers disposed in the non-display region, and the first resistor, the second resistor, the third resistor and the fourth resistor are disposed at least one of following positions: inside the shift register, between adjacent two of the plurality of shift registers, at a side of the plurality of shift registers close to the display region, and at a side of the plurality of shift registers away from the display region.

Provided are an array substrate, a display panel and a display device, and the array substrate includes: at least one pressure sensor disposed in the non-display region; and the pressure sensor includes a first resistor, a second resistor, a third resistor and a fourth resistor; and a plurality of shift registers disposed in the non-display region, and the first resistor, the second resistor, the third resistor and the fourth resistor are disposed at least one of following positions: inside the shift register, between adjacent two of the plurality of shift registers, at a side of the plurality of shift registers close to the display region, and at a side of the plurality of shift registers away from the display region.

Digital circuits, and other types of circuits, may be implemented using improved charge domain techniques based on modern silicon processing compatible with standard digital flows. An example of technology that can be used for charge domain digital flows are FINs (as used in FinFET) which can be modified to produce charge domain shift registers and charge domain digital logic. Also, novel notch based implementations which overcome limited potential range, speed, complex clocking and density issues of older generations of charge domain technology may be disclsoed. Such implementations can significantly improve performance, density and reduce power consumption of charge domain digital circuits, with the proper implants and process modifications.