Methods, systems, and devices for performing quick precharge command sequences are described. An operating mode that is associated with a command sequence having a reduced duration relative to another operating mode may be configured at a memory device. The operating mode may be configured based on determining that a procedure does not attempt to preserve or is independent of preserving a logic state of accessed memory cells, among other conditions. While operating in the mode, the memory device may perform a received precharge command using a first set of operations having a first duration—rather than a second set of operations having a second set of operations having a second, longer duration—to perform the received precharge command. The first set of operations may also use less current or introduce less disturbance into the memory device relative to the second set of operations.

An electronic device includes a masking signal generation circuit configured to generate a test masking signal by receiving a fuse data during a period in which a test masking mode is executed; and a test mode signal generation circuit configured to, when a test command for executing a test in an internal circuit is input, execute the test based on the test masking signal.

A 3D semiconductor device with a built-in-test-circuit (BIST), the device comprising: a first single-crystal substrate with a plurality of logic circuits disposed therein, wherein said first single-crystal substrate comprises a device area, wherein said plurality of logic circuits comprise at least a first interconnected array of processor logic, wherein said plurality of logic circuits comprise at least a second interconnected set of circuits comprising a first logic circuit, a second logic circuit, and a third logic circuit, wherein said second interconnected set of logic circuits further comprise switching circuits that support replacing said first logic circuit and/or said second logic circuit with said third logic circuit; and said built-in-test-circuit (BIST), wherein said first logic circuit is testable by said built-in-test-circuit (BIST), and wherein said second logic circuit is testable by said built-in-test-circuit (BIST).

The present disclosure provides an information tamper-resistant system and method. The system includes: a storage module; a writing module connected with the storage module through a first OTP switch, to write source information to the storage module; a first reading module connected with the storage module through a second OTP switch, to read out written information in the storage module and disconnect the first OTP switch and the second OTP switch after confirming that the written information is accurate; and a second reading module connected with the storage module through a third OTP switch, to read out information stored in the storage module after the third OTP switch is switched on; the first OTP switch, the second OTP switch, and the third OTP switch can only perform one switch-on operation or one switch-off operation. The system and method effectively avoid theft and tampering of information.

Testing circuitry and methods are disclosed for use with analog neural memory in deep learning artificial neural networks. In one example, a method is disclosed of testing a plurality of non-volatile memory cells in an array of non-volatile memory cells, wherein the array is arranged in rows and columns, wherein each row is coupled to a word line and each column is coupled to a bit line, and wherein each word line is selectively coupled to a row decoder and each bit line is selectively coupled to a column decoder, the method comprising asserting, by the row decoder, all word lines in the array; asserting, by the column decoder, all bit lines in the array; performing a deep programming operation on the array of non-volatile memory cells; and measuring a total current received from the bit lines.

The present disclosure relates to a memory device comprising: an array of memory cells; and an access management architecture providing a secure access to a test mode of the array of memory cells,
the access management architecture comprising: a register group comprising data identifying the memory device; a cryptographic algorithm calculating an internal signature having a mechanism for ensuring data freshness; a non volatile memory area storing specific data to be used by the cryptographic algorithm for calculating the internal signature; a comparison block for comparing the calculated internal signature with a user provided signature to generate an enable signal allowing access to a test mode of the array of memory cells.
The disclosure also relates to a System-on-Chip (SoC) component comprising a memory device as well as to a method for managing access to a memory array into a test mode.

The present disclosure relates to a memory device comprising: an array of memory cells; and an access management architecture providing a secure access to a test mode of the array of memory cells, the access management architecture comprising: a register group comprising data identifying the memory device; a cryptographic algorithm calculating an internal signature having a mechanism for ensuring data freshness; a non volatile memory area storing specific data to be used by the cryptographic algorithm for calculating the internal signature; a comparison block for comparing the calculated internal signature with a user provided signature to generate an enable signal allowing access to a test mode of the array of memory cells. The disclosure also relates to a System-on-Chip (SoC) component comprising a memory device as well as to a method for managing access to a memory array into a test mode.

A semiconductor memory device included in each of a plurality of chips which are divided by a scribe lane and formed on an upper surface of a wafer, includes a memory core and a built-in self test (BIST) circuit. The memory core includes a memory cell array that stores data and a data input/output circuit connected to a data input/output pad. The BIST circuit is connected to a test pad that is separate from the data input/output pad. The BIST circuit generates test pattern data including first parallel bits based on commands and addresses received from an external automatic test equipment (ATE) during a wafer level test process performed on the semiconductor memory device. The BIST circuit tests the memory core by applying the test pattern data to the memory cell array through the data input/output circuit.

An integrated circuit (IC) chip includes a plurality of interlayer channels; at least one data pad; an identification (ID) generation circuit suitable for generating a chip ID signal by decoding a command/address signal; a first transmission circuit suitable for transferring a plurality of internal data pieces to a transmission path by aligning a plurality of interlayer data pieces respectively transferred from the plurality of interlayer channels according to a plurality of strobe signals while selectively inverting the plurality of interlayer data pieces according to the chip ID signal; and a second transmission circuit suitable for transferring the plurality of internal data pieces from the transmission path to the at least one data pad.

A wafer-level method of testing an integrated circuit (IC) device includes: (i) applying a plurality of test operation signals to a wafer containing the IC device, (ii) generating a test enable signal in response to detecting, on the wafer, a toggling of at least one of the plurality of test operation signals, and then (iii) testing at least a portion of the IC device in response to the generating the test enable signal. The generating may also include generating a test enable signal in response to detecting, on the wafer, an inactive-to-active transition of a toggle detection signal.