A semiconductor device includes: first and second terminal switches connected correspondingly between the first and second terminals of a sense amplifier and corresponding first and second nodes; first and second recycle switches connected correspondingly between the first and second nodes and corresponding third and fourth nodes; and first and second capacitors connected correspondingly between the third and fourth nodes; and wherein the first and second recycle switches are configured to selectively connect the first and second capacitors correspondingly to the first and second nodes in phases including as follows: during a recovery phase in which first and second gleaned amounts of charge (first and second gleaned charges) are recovered from corresponding selected ones of bit lines; and during a reuse phase in which the first and second gleaned charges are reused from correspondingly onto selected corresponding ones of the array of bit lines.

A memory control circuit includes an input circuit that receives data to be written to a storage having multiple nonvolatile memory cells, and a control circuit, when a second number of bits that are included in a first bit string and having a first number of bits and have a second logical value different from a first logical value equal to initial values stored in the multiple nonvolatile memory cells is equal to or smaller than a first threshold, writes the first bit string and the first additional value to the storage, and that associates, when the second number of the bits is larger than a second threshold larger than the first threshold, a second bit string obtained by reversing logical values of all the bits of the first bit string with a second additional value and writes the second bit string and the second additional value to the storage.

A sense component of a memory device in accordance with the present disclosure may selectively employ components having a relatively high voltage isolation characteristic in a portion of the sense component associated with relatively higher voltage signals (e.g., signals associated with accessing a ferroelectric random access memory (FeRAM) cell), and components having a relatively low voltage isolation characteristic in a portion of the sense component associated with relatively lower voltage signals (e.g., input/output signals according to some memory architectures). Voltage isolation characteristics may include isolation voltage, activation threshold voltage, a degree of electrical insulation, and others, and may refer to such characteristics as a nominal value or a threshold value. In some examples the sense component may include transistors, and the voltage isolation characteristics may be based at least in part on gate insulation thickness of the transistors in each portion of the sense component.

A semiconductor device includes: first and second terminal switches connected correspondingly between the first and second terminals of a sense amplifier and corresponding first and second nodes; first and second recycle switches connected correspondingly between the first and second nodes and corresponding third and fourth nodes; and first and second capacitors connected correspondingly between the third and fourth nodes; and wherein the first and second recycle switches are configured to selectively connect the first and second capacitors correspondingly to the first and second nodes in phases including as follows: during a recovery phase in which first and second gleaned amounts of charge (first and second gleaned charges) are recovered from corresponding selected ones of bit lines; and during a reuse phase in which the first and second gleaned charges are reused from correspondingly onto selected corresponding ones of the array of bit lines.

A sense component of a memory device in accordance with the present disclosure may selectively employ components having a relatively high voltage isolation characteristic in a portion of the sense component associated with relatively higher voltage signals (e.g., signals associated with accessing a ferroelectric random access memory (FeRAM) cell), and components having a relatively low voltage isolation characteristic in a portion of the sense component associated with relatively lower voltage signals (e.g., input/output signals according to some memory architectures). Voltage isolation characteristics may include isolation voltage, activation threshold voltage, a degree of electrical insulation, and others, and may refer to such characteristics as a nominal value or a threshold value. In some examples the sense component may include transistors, and the voltage isolation characteristics may be based at least in part on gate insulation thickness of the transistors in each portion of the sense component.

A memory control circuit includes an input circuit that receives data to be written to a storage having multiple nonvolatile memory cells, and a control circuit, when a second number of bits that are included in a first bit string and having a first number of bits and have a second logical value different from a first logical value equal to initial values stored in the multiple nonvolatile memory cells is equal to or smaller than a first threshold, writes the first bit string and the first additional value to the storage, and that associates, when the second number of the bits is larger than a second threshold larger than the first threshold, a second bit string obtained by reversing logical values of all the bits of the first bit string with a second additional value and writes the second bit string and the second additional value to the storage.

A semiconductor device including: a sense amplifier; a branched line selectively connectable to the amplifier; a recycling arrangement selectively connectable to the branched line; an array of bit lines connected to corresponding memory cells; a multiplexer configured to selectively connect the branched line to a selected one of the memory cells through a corresponding line amongst the array of bit lines; and a controller configured to control the recycling arrangement and the multiplexer to perform intra-sense-amplifier recycling of a gleaned amount of charge (gleaned charge) recovered from a first read operation to a second read operation.

A sense amplifier includes a current supply unit, an amplification unit, a pass transistor and a latch unit. The current supply unit may be configured to provide a sensing current to a sensing node. The amplification unit may be configured to amplify a voltage difference between the read reference voltage with the voltage level of the global bit line. The pass transistor may be configured to transfer a current from the sensing node to the global bit line based on a signal output from the amplification unit. The latch unit may be configured to generate an output signal by detecting a voltage level change of the sensing node.

A semiconductor device including: a sense amplifier; a branched line selectively connectable to the amplifier; a recycling arrangement selectively connectable to the branched line; an array of bit lines connected to corresponding memory cells; a multiplexer configured to selectively connect the branched line to a selected one of the memory cells through a corresponding line amongst the array of bit lines; and a controller configured to control the recycling arrangement and the multiplexer to perform intra-sense-amplifier recycling of a gleaned amount of charge (gleaned charge) recovered from a first read operation to a second read operation.

A sense amplifier includes a current supply unit, an amplification unit, a pass transistor and a latch unit. The current supply unit may be configured to provide a sensing current to a sensing node. The amplification unit may be configured to amplify a voltage difference between the read reference voltage with the voltage level of the global bit line. The pass transistor may be configured to transfer a current from the sensing node to the global bit line based on a signal output from the amplification unit. The latch unit may be configured to generate an output signal by detecting a voltage level change of the sensing node.