The disclosed technology provides an electronic device includes a semiconductor memory that includes a first contact plug over a substrate; an interlayer dielectric layer located over the first contact plug and having a hole which exposes at least a portion of the first contact plug; a first electrode layer formed along a sidewall and a bottom surface of the hole to be in contact with the first contact plug; a variable resistance layer over the first electrode layer and structured to include (1) a first portion that extends along the sidewall of the hole in a direction perpendicular to the substrate and exhibits a variable resistance and (2) a second portion that is parallel to the bottom surface of the hole and does not exhibit a variable resistance, and a second electrode layer formed over the variable resistance layer.

Providing for three-dimensional memory cells having enhanced electric field characteristics and/or memory cells located at broken interconnects is described herein. By way of example, a two-terminal memory cell can be constructed from a layered stack of materials, where respective layers are arranged along a direction that forms a non-zero angle to a normal direction of a substrate surface upon which the layered stack of materials is constructed. In some aspects, the direction can be orthogonal to or substantially orthogonal to the normal direction. In other aspects, the direction can be less than orthogonal to the normal direction. Where an internal angle of the memory cell forms a non-orthogonal angle, an enhanced electric field or current density can result, providing improved switching times and memory performance.

Providing for three-dimensional memory cells having enhanced electric field characteristics and/or memory cells located at broken interconnects is described herein. By way of example, a two-terminal memory cell can be constructed from a layered stack of materials, where respective layers are arranged along a direction that forms a non-zero angle to a normal direction of a substrate surface upon which the layered stack of materials is constructed. In some aspects, the direction can be orthogonal to or substantially orthogonal to the normal direction. In other aspects, the direction can be less than orthogonal to the normal direction. Where an internal angle of the memory cell forms a non-orthogonal angle, an enhanced electric field or current density can result, providing improved switching times and memory performance.

A memory device for thermoelectric heat confinement and method for producing same. The memory device includes a plurality of phase-change memory cells, wherein each of the phase-change memory cells has a first electrode, a second electrode and a phase-change material. The first electrode and the phase-change material are arranged such that a surface normal of a dominating interface for a current flow between the first electrode and the phase-change material points on one side to the phase-change material of the phase-change memory cell and on an opposite side to a phase-change material of a neighboring phase-change memory cell. A method for producing a memory device for thermoelectric heat confinement is also provided.

A hybrid switch and memory cell includes a transistor device that has an atomically-thin semiconductor material channel, source/drain electrodes, and gate dielectric. The cell includes a resistive-random-access-memory having a thin conductive edge and a 2D insulator layer over the thin conductive edge, wherein the 2D insulator layer extends over the semiconductor channel and serves as the gate dielectric in the transistor device.