A memory cell, e.g., a flash memory cell, includes a substrate, a flat-topped floating gate formed over the substrate, and a flat-topped oxide region formed over the flat-topped floating gate. The flat-topped floating gate may have a sidewall with a generally concave shape that defines an acute angle at a top corner of the floating gate, which may improve a program or erase efficiency of the memory cell. The flat-topped floating gate and overlying oxide region may be formed with without a floating gate thermal oxidation that forms a conventional football oxide. A word line and a separate erase gate may be formed over the floating gate and oxide region. The erase gate may overlap the floating gate by a substantially greater distance than the word line overlaps the floating gate, which may allow the program and erase coupling to the floating gate to be optimized independently.

This disclosed technology relates to a programmable NAND flash memory and a method for operating the NAND flash memory. The method comprises applying a first voltage to the first gate and a pass voltage to one or more word lines to allow charge to inject into the channel layer and form charge packets. Each charge packet can be arranged next to one of the second gates. The method further comprises applying a programming voltage to the word lines to move the charge packets from the channel layer into the memory cells associated with the second gates next to which they are arranged.

A memory cell, e.g., a flash memory cell, includes a substrate, a flat-topped floating gate formed over the substrate, and a flat-topped oxide region formed over the flat-topped floating gate. The flat-topped floating gate may have a sidewall with a generally concave shape that defines an acute angle at a top corner of the floating gate, which may improve a program or erase efficiency of the memory cell. The flat-topped floating gate and overlying oxide region may be formed with without a floating gate thermal oxidation that forms a conventional football oxide. A word line and a separate erase gate may be formed over the floating gate and oxide region. The erase gate may overlap the floating gate by a substantially greater distance than the word line overlaps the floating gate, which may allow the program and erase coupling to the floating gate to be optimized independently.

Some embodiments include apparatuses, and methods of operating the apparatuses. Some of the apparatuses include a data line, a first memory cell string including first memory cells located in different levels of the apparatus, first access lines to access the first memory cells, a first select gate coupled between the data line and the first memory cell string, a first select line to control the first select gate, a second memory cell string including second memory cells located in different levels of the apparatus, second access lines to access the second memory cells, the second access lines being electrically separated from the first access lines, a second select gate coupled between the data line and the second memory cell string, a second select line to control the second select gate, and the first select line being in electrical contact with the second select line.

Some embodiments include apparatuses, and methods of operating the apparatuses. Some of the apparatuses include a data line, a first memory cell string including first memory cells located in different levels of the apparatus, first access lines to access the first memory cells, a first select gate coupled between the data line and the first memory cell string, a first select line to control the first select gate, a second memory cell string including second memory cells located in different levels of the apparatus, second access lines to access the second memory cells, the second access lines being electrically separated from the first access lines, a second select gate coupled between the data line and the second memory cell string, a second select line to control the second select gate, and the first select line being in electrical contact with the second select line.

Disclosed is an improved method for operating a program of a three-dimensional flash memory. A program voltage has a value obtained by adding a step voltage to a previous program voltage applied in a previous program operation, and the step voltage is increased as a program operation is repeated. Also, the program operation is performed on a target memory cell by applying a negative voltage to a bit line of a selected cell string and applying the program voltage to a selected word line. In addition, tunneling oxide-charge trap nitride-blocking oxide (ONO) formed surrounding a vertical channel pattern is included, and at least one of a tunneling oxide layer or a blocking oxide layer of the ONO is formed of a ferroelectric material.

A non-volatile semiconductor memory device in which, while voltage from a first control line is applied, as a memory gate voltage, to a sub control line through a switching transistor, another switching transistor can block voltage application to a corresponding sub control line. Thus, while a plurality of memory cells are arranged in one direction along the first control line, the number of memory cells to which a memory gate voltage is applied can reduced by the switching transistor, which reduces the occurrence of disturbance, accordingly. The sub control line to which the memory gate voltage is applied from the first control line is used as the gates of memory transistors, and thus the sub control line and the gates are disposed in a single wiring layer, thereby achieving downsizing as compared to a case in which the sub control line and the gates are disposed in separate wiring layers.

A memory device applies voltage to drain select lines, which are determined individually. A program operation control unit applies a precharge voltage to a drain select line coupled to a cell string selected from the first cell string and the second cell string before a program voltage is applied to the word line, during a time determined depending on a resistance value of the drain select line coupled to the selected cell string.

A semiconductor memory device includes first and second semiconductor pillars, a first string including first memory cells connected in series and a second string including second memory cells connected in series on opposite sides of the first semiconductor pillar, respectively, a third string including third memory cells connected in series and a fourth string including fourth memory cells connected in series, on opposite sides of the second semiconductor pillar, respectively, first word lines, second word lines, and a driver configured to supply different voltages to the first and second word lines during an erasing operation to erase data in the second and fourth memory cells. In the erasing operation, the driver supplies a first voltage higher than a reference voltage to the first word lines, and supplies the reference voltage to the second word lines.

Disclosed are NOR memory array, NOR memory and electronic device. The NOR memory array comprises: multiple vertical memory groups arranged in n rows and m columns on a horizontal plane, one vertical memory group includes at least h vertically stacked memory transistors, where n, m, and h are natural numbers greater than 1, wherein, the memory transistors in one vertical memory group share a vertically extended columnar gate structure, part or all of columnar gate structures of vertical memory groups in a same row are connected to a same word line, part or all of memory transistors located at a same stack layer in vertical memory groups in a same column are connected to a same bit line, and an isolation part, for isolating active areas and bit lines of the memory transistors in the adjacent columns, is arranged between adjacent columns of the vertical memory groups.