Some embodiments include apparatuses, and methods of operating the apparatuses. Some of the apparatuses include a data line, a first memory cell string including first memory cells located in different levels of the apparatus, first access lines to access the first memory cells, a first select gate coupled between the data line and the first memory cell string, a first select line to control the first select gate, a second memory cell string including second memory cells located in different levels of the apparatus, second access lines to access the second memory cells, the second access lines being electrically separated from the first access lines, a second select gate coupled between the data line and the second memory cell string, a second select line to control the second select gate, and the first select line being in electrical contact with the second select line.

Provided are a non-volatile memory device and a method of fabricating the same. The non-volatile memory includes a channel layer; a data storage layer disposed on the channel layer; a plurality of control gates arranged on the data storage layer and spaced apart from one another; and one or more sub-gates, at least one of the sub-gates being arranged between two adjacent control gates.

Provided are a non-volatile memory device and a method of fabricating the same. The non-volatile memory includes a channel layer; a data storage layer disposed on the channel layer; a plurality of control gates arranged on the data storage layer and spaced apart from one another; and one or more sub-gates, at least one of the sub-gates being arranged between two adjacent control gates.

A semiconductor memory device includes a memory pillar; first and second conductive layers on either side of the memory pillar; third and fourth conductive layers and fifth and sixth conductive layer respectively below and above first and second conductive layers; seventh and eighth conductive layers below third and fourth conductive layers; ninth and tenth conductive layers above fifth and sixth conductive layers; memory cells formed between a respective first through tenth conductive layers and the memory pillar; and a control circuit, which applies a read voltage to the first conductive layer, a negative voltage to second, fourth, and sixth conductive layers, and a read pass voltage to other conductive layers, applies the read pass voltage to first, second, fourth, and sixth conductive layers, applies a ground voltage or lower to a first group of conductive layers, and then a ground voltage to a second group of conductive layers.

Some embodiments include apparatuses, and methods of operating the apparatuses. Some of the apparatuses include a data line, a first memory cell string including first memory cells located in different levels of the apparatus, first access lines to access the first memory cells, a first select gate coupled between the data line and the first memory cell string, a first select line to control the first select gate, a second memory cell string including second memory cells located in different levels of the apparatus, second access lines to access the second memory cells, the second access lines being electrically separated from the first access lines, a second select gate coupled between the data line and the second memory cell string, a second select line to control the second select gate, and the first select line being in electrical contact with the second select line.

A method for determining an optimal voltage pulse for programming a flash memory cell, the optimal voltage pulse being defined by a voltage ramp from a non-zero initial voltage level during a programming duration, wherein the method takes into account a set of parameters including a programming window target value and a drain current target value of the memory cell.

Embodiments the present disclosure provide a MTP memory cell and methods for forming the same. The MTP memory cell includes a FinFET transistor having a storage node formed around the channel region and a metal gate electrode around the storage node. The memory cell may be implemented by either n-channel transistor or p-channel transistor.

Methods and apparatuses are contemplated herein for enhancing the efficiency of nonvolatile memory devices. In an example embodiment, a nonvolatile memory device comprises a substrate and 3D array of nonvolatile memory cells, the 3D array including a plurality of conductive layers, separated from each other by insulating layers, the plurality of conductive layers comprising a top layer, the top layer comprising n string select lines (SSLs) and one or more bottom layers, the top layer further comprises n1 cuts, each cut electrically separating two SSLs, wherein each cut is cut to a depth of the top layer and not extending into the bottom layers and a plurality of vertical channels arranged orthogonal to the plurality of layers, each of the plurality of channels comprising a string of memory cells, each of plurality of strings coupled to a bit line, an SSL and one or more word lines.

As block sizes in NAND memory continue to increase in size and density, in can be useful to access less than all of the block, such as sub-block or subset of the blocks NAND strings, in order to reduce read disturbs, reduce power consumption, and increase operating speeds. Although this sort of separation of sub-block can be achieved by independently biasable select gates, the sort of select gate structure can face processing difficulties, particularly at the source side of three dimensional NAND structures. To avoid these difficulties while still providing individually selectable sub-blocks, the following introduces word line based selectors, where multiple word lines of a blocks are programmed with different sets of threshold voltages, allowing them to be biased for individual access of sub-blocks.

A semiconductor storage device according to one embodiment includes a multi-layered body and a columnar body. The multi-layered body includes a plurality of gate electrode layers and a plurality of insulating layers.