Patent classifications
G11C2216/12
Three-dimensional one-time-programmable memory comprising dummy bit lines
A multi-bit-per-cell three-dimensional read-only memory (3D-OTP.sub.MB) comprises a plurality of dummy bit lines. It comprises a plurality of OTP cells stacked above a semiconductor substrate. Each OTP array comprises at least four dummy bit lines.
SOLID STATE STORAGE DEVICE AND READ TABLE MANAGEMENT METHOD THEREOF
A read table management method for a solid state storage device includes the following steps. If the lowest computation value in a hot group is lower than the highest computation value in a cold group when a read table adjusting process is enabled, a first read voltage set corresponding to the lowest computation value in the hot group and a second read voltage set corresponding to the highest computation value in the cold group are swapped with each other. Consequently, the second read voltage set becomes to belong to the hot group, and the first read voltage set becomes to belong to the cold group.
Three-Dimensional One-Time-Programmable Memory With A Dummy Word Line
To reduce the pre-programming cost, an efficient three-dimensional one-time-programmable read-only memory (3D-OTP) is disclosed. It comprises a dummy word line and a plurality of dummy bit lines. Only the dummy OTP cells at the intersections of the dummy word line and dummy bit lines are programmed. All other dummy OTP cells are unprogrammed.
Double-Biased Three-Dimensional One-Time-Programmable Memory
To reduce the pre-programming cost, a double-biased three-dimensional one-time-programmable read-only memory (3D-OTP) is disclosed. The OTP array comprises a dummy word line and a plurality of data word lines. During read, both voltages on the dummy word line and a selected data word line are raised.
Three-Dimensional One-Time-Programmable Memory Comprising Dummy Bit Lines
The present invention discloses a multi-bit-per-cell three-dimensional read-only memory (3D-OTP.sub.MB) comprising a plurality of dummy bit lines. It comprises a plurality of OTP cells stacked above a semiconductor substrate. Each OTP array comprises at least four dummy bit lines.
Multi-bit-per-cell three-dimensional one-time-programmable memory
A multi-bit-per-cell three-dimensional read-only memory (3D-OTP.sub.MB) comprises a plurality of OTP cells stacked above a semiconductor substrate. Each OTP cell comprises an antifuse layer, which is irreversibly switched from a high-resistance state to a low-resistance state during programming. By adjusting the programming current, the programmed antifuses have different resistances.
LARGE MEMORY WINDOW VERTICAL NAND FERROELECTRIC CHARGE PUMPING FIELD EFFECT TRANSISTOR FOR HIGH-DENSITY AND LOW-POWER STORAGE
A nonvolatile memory device is disclosed that incorporates a FeFET having a gate stack with a ferroelectric dielectric layer positioned below a charge trapping layer. During programming, polarization switching in the ferroelectric layer drives charge injection from the gate into the overlying trapping layer. The trapped charge combines with the ferroelectric polarization to shift the threshold voltage of the device. A capping dielectric may be included above the trapping layer to improve charge retention. This gate-side charge injection mechanism supports efficient programming while maintaining a compact vertical stack suitable for integration into high-density memory architectures such as vertical NAND.