An apparatus and method for current peak detection. The apparatus includes a pulse laser diode array, a sense resistor, a capacitive voltage divider (CVD) electrically coupled to the pulse laser diode array, a first current rectifier, a second current rectifier, a first current peak detector, a second current peak detector, an analog-to-digital converter (ADC) operable to convert the analog outputs from each current peak detector to a digital output signal, and a digital signal processing (DSP) unit operable to detect, from the digital output signal, a current peak pulse at the top and the bottom of the sense resistor.

A method for synchronizing signals of a plurality of participants. A relationship between the signals is given by a physical relation. The signals are each filtered with a first filter in order to determine a shift between the signals. The determined shift is a measure of the phase shift between the signals. The shift is subsequently eliminated by filtering the signals respectively with a second filter.

An electrical current measurement circuit is provided. The electrical current measurement circuit is configured to receive a sense current proportionally related to an electrical current of interest to continuously charge a capacitor to a sense voltage. The electrical current measurement circuit is configured to determine whether the sense voltage reaches a predefined voltage threshold and reduce the sense voltage to below the predefined voltage threshold in response to the sense voltage reaching the predefined voltage threshold. The electrical current measurement circuit counts each occurrence of the sense voltage reaching the predefined voltage threshold and quantifies the electrical current based on a total count of the sense voltage reaching the predefined voltage threshold during the predefined measurement period. By incorporating the electrical current measurement circuit in an electronic device, it may be possible to accurately monitor and thus help to optimize power consumption and battery life of the electronic device.

It is provided a current recording method, a current recording device and a current recording system by the embodiments of this disclosure. The current recording method comprises: acquiring a first current Fourier value, the first current Fourier value being a Fourier value acquired by Fourier transforming an instantaneous value of current at a first end of a power line; acquiring a second current Fourier value, the second current Fourier value being a Fourier value acquired by Fourier transforming an instantaneous value of current at a second end of the power line; time-alignment the first current Fourier value and the second current Fourier value, based on a first transmission delay for acquiring the first current Fourier value and a second transmission delay for acquiring the second current Fourier value; storing the aligned first current Fourier value and second current Fourier value into a storage.

A arrangement is disclosed for an on-chip system having an increased resolution for supply voltage measurements. The system includes a phase locked loop (PLL), a divider, and a timer. The PLL is configured to generate an oscillator signal. The divider is configured to divide the oscillator signal to generate an divided clock signal. The timer is configured to generate an application start signal and an analog to digital converter (ADC) start signal based on the oscillator signal and a timer delay (Tdelay). The timer delay (Tdelay) is based on the application start signal and the ADC start signal.

An antenna alignment device includes an embedded (or is connected to) direct current (DC) voltmeter. In addition to using different sensors for azimuth and tilt alignment of an antenna, the DC voltmeter may be used to measure the DC voltage indicative of received signal strength at the antenna. The received signal may have a transmission pattern generated by a far side antenna. Particularly, the DC voltmeter may be used to detect peaks in the DC voltage and count the number of detected peaks as the antenna is moved changing its azimuth and the tilt. An odd number of peaks indicates the boresight of the antenna is in the main lobe of the transmission pattern, and an even number of peaks indicates otherwise. The highest peak in the odd number of peaks corresponds to the main lobe and the boresight of the antenna is aligned/tuned toward the highest peak.

The response of a coil based current measuring circuit is often proportional to frequency. To correct for this a low pass or integrating function is applied to the response to linearize it. The low pass filter is made from real resistors and capacitors, and tolerances in their values significantly affect the estimate of current. The present approach can provide a way of addressing such problems. This allows consumers of electricity to have confidence in the accuracy of, for example, their electricity meter.

An energy monitoring device includes a power supply circuit electrically coupled to a power source via a hot conductor and a load via a load conductor; a relay circuit including a relay and a relay driver circuit, where the relay includes a plurality of coils and the relay contact electrically coupled to the hot conductor and the load conductor; a sensing circuit including a hot voltage sensor and a load voltage sensor; and a controller electrically coupled to the power supply circuit, the relay driver circuit, and the sensing circuit, and structured to receive a hot voltage from the hot voltage sensor and a load voltage from the load voltage sensor, and determine a load current based at least in part on a relay contact resistance of the relay contact and a delta between the hot voltage and the load voltage.

A resistor network with reduced area and/or improved voltage resolution and methods of designing and operating the same are provided. Generally, the resistor network includes a resistor ladder with a first number (n) of integrated resistors coupled in series between a top and a bottom contact, with one or more contacts coupled between adjacent resistors. A second number of integrated resistors is coupled in parallel between the top and bottom contacts, and a third number of integrated resistors is coupled in series between the second integrated resistors and either the top or the bottom contact. Each of the integrated resistors has a resistance of R, and a voltage developed across each resistor in the resistor ladder is equal to a voltage applied between the top and bottom contacts divided by n. Where the second number is n−1, and the third number is 1, the total number of resistors is 2n.

A voltage-glitch detection and protection circuit and method are provided. Generally, circuit includes a voltage-glitch-detection-block (GDB) and a system-reset-block coupled to the GDB to generate a reset-signal to cause devices in a chip including the circuit to be reset when a voltage-glitch in a supply voltage (VDD) is detected. The GDB includes a voltage-glitch-detector coupled to a latch. The voltage-glitch-detector detects the voltage-glitch and generates a PULSE to the system-reset-block and latch. The latch receives the PULSE and generates a PULSE_LATCHED signal to the system-reset-block to ensure the reset-signal is generated no matter a width of the PULSE. In one embodiment, the latch includes a filter and a sample and hold circuit to power the latch, and ensure the PULSE_LATCHED signal is coupled to the system-reset-block when a voltage to the GDB or to the latch drops below a minimum voltage due to the voltage-glitch.