A method of determining a signal histogram having a predetermined number of bins. The method includes: receiving an input signal; decimating the input signal, thereby generating a decimated signal that includes a maximum signal value and a minimum signal value associated with the maximum signal value; assigning the maximum signal value to a maximum bin of a signal histogram; assigning the minimum signal value to a minimum bin of the signal histogram; and filling at least one intermediate bin of the signal histogram with an intermediate value, wherein the intermediate bin is located between the minimum bin and the maximum bin in the signal histogram.

Improved determination of a trigger time. For this purpose, an input signal is provided to multiple low pass filters having different bandwidths. A trigger event is detected in each of the low pass filtered signals and a corresponding trigger time is determined. The trigger time which is determined based on valid trigger detection and provided by the low pass filter with the highest bandwidth is used for further analysis.

An analog fault detection circuit is disclosed. The analog fault detection circuit comprises an input terminal, an input circuit path coupled to the input terminal at a first end and a first sampling switch coupled to the second end of the input circuit path. The first sampling switch is configured to sample an input path voltage at the second end of the input circuit path to provide a first analog to digital converter (ADC) input voltage. The analog fault detection circuit further comprises a first ADC conversion circuit configured to convert the first ADC input voltage to a first digital ADC output; and a first broken wire detection circuit coupled between the first sampling switch and the first ADC conversion circuit, and configured to adaptively pulldown or pullup the first ADC input voltage, in order to detect a fault associated with a first analog circuit path.

The current measurement device (1, 2) includes a first sensor (SE1) configured to detect a direct current magnetic field and a low-frequency alternating current magnetic field generated due to the current (1) flowing through the conductor (MC) to be measured, a second sensor (SE2) configured to detect alternating current magnetic fields from a low frequency to a high frequency generated due to the current (1) flowing through the conductor to be measured, a first calculator (21, 21A) configured to calculate the current flowing through the conductor to be measured from a detection result of the first sensor using distance information indicating a distance (r) between the first sensor (SE1) and the conductor (MC) to be measured, a second calculator (22) configured to calculate the current flowing through the conductor to be measured from a detection result of the second sensor, and a synthesizer (23) configured to synthesize a calculation result of the first calculator with a calculation result of the second calculator.

An analog fault detection circuit is disclosed. The analog fault detection circuit comprises an input terminal, an input circuit path coupled to the input terminal at a first end and a first sampling switch coupled to the second end of the input circuit path. The first sampling switch is configured to sample an input path voltage at the second end of the input circuit path to provide a first analog to digital converter (ADC) input voltage. The analog fault detection circuit further comprises a first ADC conversion circuit configured to convert the first ADC input voltage to a first digital ADC output; and a first broken wire detection circuit coupled between the first sampling switch and the first ADC conversion circuit, and configured to adaptively pulldown or pullup the first ADC input voltage, in order to detect a fault associated with a first analog circuit path.

SOGI based apparatus and methods for providing balanced three phase output signals free of harmonics, DC components and imbalance present in the input signals, are disclosed. In addition, such apparatus and methods for providing corresponding output signals which are drift-free integrals of the input signals and which signals may enable the control of a power electronics inverter for improved and robust grid power injection and for motor control are disclosed.

An amplification interface includes an input terminal receiving a sensor current and an output terminal supplying an output voltage. An analog integrator is connected to the input terminal and supplies the output voltage. A current generator is connected to the input of the analog integrator and generates a compensation current based on a drive signal. A control circuit generates the drive signal for the current generator based on a control signal representing an offset in the sensor current supplied by the sensor. The current generator generates, based on the driving signal, a positive or negative current. The control circuit determines a first duration and a second duration as a function of the control signal representing the offset in the sensor current, during the measurement interval, and sets the driving signal to a first logic value for the first duration and to a second logic value for the second duration.

A circuit includes a tank capacitor coupled between first and second nodes, and a sense resistor having a first terminal coupled to the first node and a second terminal coupled to a regulator input. A switching circuit has first and second inputs coupled to the first and second terminals of the sense resistor. A gain stage has first and second inputs capacitively coupled to first and second outputs of the switching circuit. An analog-to-digital converter receives the output of the gain stage, and receives first and second differential voltages. A reference voltage generator has a temperature independent current source coupled to source current to a reference resistor, the first differential reference voltage being formed across the reference resistor. The reference resistor and sense resistor are located sufficiently close to one another on a single common substrate such that they remain at substantially a same temperature.

A system and method for protecting against a voltage glitch are provided. Generally, the system includes a reset-detector coupled to a supply voltage (VCC) and to a power-on-reset (POR) block, and a glitch-detector coupled to VCC and the reset-detector. The reset-detector is operable to provide a signal to the POR block to generate a global-reset-signal when VCC decreases below a minimum and remains low for at least a first time. The glitch-detector is operable to provide a glitch-signal to the reset-detector to cause it to provide the signal to the POR block when VCC decreases below the minimum and remains low for at least a second time, where the second time is less than the first. The reset-detector can further include a retention-circuit operable to recall a glitch-signal was received and signal the POR block when VCC is restored. Other embodiments are also disclosed.

A circuit configured to sense an input analog signal generated by a sensor at a first frequency and to generate an output digital signal indicative of the sensed input analog signal. The circuit includes a conditioning circuit, an ADC, a feedback circuit, and a low-pass filter. The conditioning circuit is configured to receive the input analog signal and to generate a conditioned analog signal. The ADC is configured to provide a converted digital signal based on the conditioned analog signal. The feedback circuit includes a band-pass filter configured to selectively detect a periodic signal at a second frequency higher than the first frequency and to act on the conditioning circuit to counter variations of the periodic signal at the second frequency. The low-pass filter is configured to filter out the periodic signal from the converted digital signal to generate the output digital signal.