A real-time power monitoring method executable by an electronic device, comprising: performing an ADC calibration operation to a voltage of a first battery of the electronic device; calculating and forming a diagonal line for the first battery; determining whether the comparison result between a gain and an offset and an optimum gain and an optimum offset is located with a preset error range; if the comparison result is located with the preset error range, determining that the voltage calibration for the first battery is successful; and, if the comparison result is located outside the preset error range, determining that the voltage calibration for the first battery is unsuccessful, analyzing and fixing the first battery and for re-performing the ADC calibration to the first battery.

A real-time power monitoring method executable by an electronic device, comprising: performing an ADC calibration operation to a voltage of a first battery of the electronic device; calculating and forming a diagonal line for the first battery; determining whether the comparison result between a gain and an offset and an optimum gain and an optimum offset is located with a preset error range; if the comparison result is located with the preset error range, determining that the voltage calibration for the first battery is successful; and, if the comparison result is located outside the preset error range, determining that the voltage calibration for the first battery is unsuccessful, analyzing and fixing the first battery and for re-performing the ADC calibration to the first battery.

A arrangement is disclosed for an on-chip system having an increased resolution for supply voltage measurements. The system includes a phase locked loop (PLL), a divider, and a timer. The PLL is configured to generate an oscillator signal. The divider is configured to divide the oscillator signal to generate an divided clock signal. The timer is configured to generate an application start signal and an analog to digital converter (ADC) start signal based on the oscillator signal and a timer delay (Tdelay). The timer delay (Tdelay) is based on the application start signal and the ADC start signal.

A arrangement is disclosed for an on-chip system having an increased resolution for supply voltage measurements. The system includes a phase locked loop (PLL), a divider, and a timer. The PLL is configured to generate an oscillator signal. The divider is configured to divide the oscillator signal to generate an divided clock signal. The timer is configured to generate an application start signal and an analog to digital converter (ADC) start signal based on the oscillator signal and a timer delay (Tdelay). The timer delay (Tdelay) is based on the application start signal and the ADC start signal.

A method for fail-safe provision of an analog output value for a control process designed for functional safety, wherein the output value is specified by a control unit as a digital output value and, in a first step, the digital output value is converted into the analog output value via a converter, in a second step, the analog output value is converted into a fail-safe digital output value using fail-safe criteria via a read-back device and, in a third step, the originally provided digital output value is compared with the converted fail-safe digital output value, where in the event of the comparison revealing a deviation or of a plausibility criterion being infringed, a safety action is performed, otherwise, the analog output value is output to the control process with the aid of a release device.

A method for fail-safe provision of an analog output value for a control process designed for functional safety, wherein the output value is specified by a control unit as a digital output value and, in a first step, the digital output value is converted into the analog output value via a converter, in a second step, the analog output value is converted into a fail-safe digital output value using fail-safe criteria via a read-back device and, in a third step, the originally provided digital output value is compared with the converted fail-safe digital output value, where in the event of the comparison revealing a deviation or of a plausibility criterion being infringed, a safety action is performed, otherwise, the analog output value is output to the control process with the aid of a release device.

An electronic circuit according to an embodiment includes a clock generator, a delay element, a first electromagnetic coupler, a first frequency converter, a second electromagnetic coupler, a second frequency converter, a controller and an output device. The clock generator is configured to generate a first clock signal. The delay element is configured to output a second clock signal which has a phase delayed with respect to the first clock signal. The first electromagnetic coupler is configured to transmit one of the first and second clock signals by electromagnetic coupling. The first frequency converter is driven by the one of the first and second clock signals transmitted from the first electromagnetic coupler and is configured to convert a first input signal to a first signal with a first frequency corresponding to the one of the first and second clock signals.

An electronic circuit according to an embodiment includes a clock generator, a delay element, a first electromagnetic coupler, a first frequency converter, a second electromagnetic coupler, a second frequency converter, a controller and an output device. The clock generator is configured to generate a first clock signal. The delay element is configured to output a second clock signal which has a phase delayed with respect to the first clock signal. The first electromagnetic coupler is configured to transmit one of the first and second clock signals by electromagnetic coupling. The first frequency converter is driven by the one of the first and second clock signals transmitted from the first electromagnetic coupler and is configured to convert a first input signal to a first signal with a first frequency corresponding to the one of the first and second clock signals.

An electronic device for monitoring an electrical quantity out of a voltage and arc intensity relative to an alternating current flowing in an electrical conductor, includes a measurement module configured to measure at least one value of the electrical quantity, a wireless transceiver, and a transmission module linked to the wireless transceiver. The monitoring device furthermore includes a computation module configured to compute at least one parameter for monitoring the electrical quantity as a function of at least one measured value of the electrical quantity, each monitoring parameter being chosen from an angular phase of the electrical quantity and a modulus of the electrical quantity, the transmission module being configured to transmit, to another electronic device, a data message containing at least one computed monitoring parameter.

An electronic device for monitoring an electrical quantity out of a voltage and arc intensity relative to an alternating current flowing in an electrical conductor, includes a measurement module configured to measure at least one value of the electrical quantity, a wireless transceiver, and a transmission module linked to the wireless transceiver. The monitoring device furthermore includes a computation module configured to compute at least one parameter for monitoring the electrical quantity as a function of at least one measured value of the electrical quantity, each monitoring parameter being chosen from an angular phase of the electrical quantity and a modulus of the electrical quantity, the transmission module being configured to transmit, to another electronic device, a data message containing at least one computed monitoring parameter.