The present disclosure relates to a sensor system, comprising a microcontroller, at least one sensor chip designed to measure a physical quantity, wherein the microcontroller and the sensor chip are coupled to one another via at least one analog signal interface for conveying analog measurement data between the sensor chip and the microcontroller and via a bidirectional digital signal interface for conveying digital secondary information between the sensor chip and the microcontroller.

The present disclosure relates to a sensor system, comprising a microcontroller, at least one sensor chip designed to measure a physical quantity, wherein the microcontroller and the sensor chip are coupled to one another via at least one analog signal interface for conveying analog measurement data between the sensor chip and the microcontroller and via a bidirectional digital signal interface for conveying digital secondary information between the sensor chip and the microcontroller.

Mutual inductance-type current sensing apparatus (1) is described which includes a mutual inductance current sensor (11) having a first transfer function. The apparatus (1) also includes a low-pass filter (12) which receives a signal from the current sensor (11). The low-pass filter (12) has a second transfer function configured to attenuate one or more harmonic components of the signal. The apparatus (1) also includes an analogue-to-digital converter (13) which receives and digitises a filtered signal output from the low-pass filter. The apparatus (1) also includes a controller (8) configured to process a digitised signal from the analogue-to-digital converter (13) using a digital processing chain configured to compensate for the frequency and phase responses of the first transfer function and the second transfer function.

Mutual inductance-type current sensing apparatus (1) is described which includes a mutual inductance current sensor (11) having a first transfer function. The apparatus (1) also includes a low-pass filter (12) which receives a signal from the current sensor (11). The low-pass filter (12) has a second transfer function configured to attenuate one or more harmonic components of the signal. The apparatus (1) also includes an analogue-to-digital converter (13) which receives and digitises a filtered signal output from the low-pass filter. The apparatus (1) also includes a controller (8) configured to process a digitised signal from the analogue-to-digital converter (13) using a digital processing chain configured to compensate for the frequency and phase responses of the first transfer function and the second transfer function.

Disclosed herein are systems and methods of calculating and mitigating time delays for electric power system samples received by remote data acquisition unit (RDAU), digitized, and transmitted to a receiving intelligent electronic device (IED). The IED may calculate time delays for various RDAUs, and establish wait windows for certain protection operations based on the samples needed for the protection operation and the calculated time delays for the various RDAUs. The IED may detect and report system or time signal anomalies based on changes to the calculated time delays from particular RDAUs.

Disclosed herein are systems and methods of calculating and mitigating time delays for electric power system samples received by remote data acquisition unit (RDAU), digitized, and transmitted to a receiving intelligent electronic device (IED). The IED may calculate time delays for various RDAUs, and establish wait windows for certain protection operations based on the samples needed for the protection operation and the calculated time delays for the various RDAUs. The IED may detect and report system or time signal anomalies based on changes to the calculated time delays from particular RDAUs.

A arrangement is disclosed for an on-chip system having an increased resolution for supply voltage measurements. The system includes a phase locked loop (PLL), a divider, and a timer. The PLL is configured to generate an oscillator signal. The divider is configured to divide the oscillator signal to generate an divided clock signal. The timer is configured to generate an application start signal and an analog to digital converter (ADC) start signal based on the oscillator signal and a timer delay (Tdelay). The timer delay (Tdelay) is based on the application start signal and the ADC start signal.

A arrangement is disclosed for an on-chip system having an increased resolution for supply voltage measurements. The system includes a phase locked loop (PLL), a divider, and a timer. The PLL is configured to generate an oscillator signal. The divider is configured to divide the oscillator signal to generate an divided clock signal. The timer is configured to generate an application start signal and an analog to digital converter (ADC) start signal based on the oscillator signal and a timer delay (Tdelay). The timer delay (Tdelay) is based on the application start signal and the ADC start signal.

The present invention relates to a circuit failure detector comprising: an input terminal for receiving a detection signal having a first frequency from an interlock circuit; a correction circuit for correcting the voltage of the received detection signal; a first comparator comparing the corrected detection signal with a first reference voltage and outputting a high voltage signal or a low voltage signal; a second comparator inverting the corrected detection signal, comparing the inverted detection signal with a second reference voltage, and outputting the high voltage signal or the low voltage signal; a counting signal generator for generating a counting signal having a second frequency; a first coupler for coupling an output signal of the first comparator with the counting signal; a second coupler for coupling the output signal of the second comparator with the counting signal; and a controller for detecting a circuit failure on the basis of the output signal of the first coupler and the output signal of the second coupler.

The present invention relates to a circuit failure detector comprising: an input terminal for receiving a detection signal having a first frequency from an interlock circuit; a correction circuit for correcting the voltage of the received detection signal; a first comparator comparing the corrected detection signal with a first reference voltage and outputting a high voltage signal or a low voltage signal; a second comparator inverting the corrected detection signal, comparing the inverted detection signal with a second reference voltage, and outputting the high voltage signal or the low voltage signal; a counting signal generator for generating a counting signal having a second frequency; a first coupler for coupling an output signal of the first comparator with the counting signal; a second coupler for coupling the output signal of the second comparator with the counting signal; and a controller for detecting a circuit failure on the basis of the output signal of the first coupler and the output signal of the second coupler.