The invention relates to a frequency multiplying device for determination of a fundamental frequency f of an analogue target signal. The device comprises a generating device for generating a reference signal having a frequency f.sub.osc, wherein f.sub.osc is greater than f, and a first counter being coupled to a terminal, the terminal to be fed with the analogue target signal, and being coupled to the generating device such that the first counter counts a number of signal edges generated from the reference signal in a time interval corresponding substantially to 1/f and outputs a first counter signal, wherein a frequency divider is coupled between the generating device and the first counter and a second counter is coupled to the generating device for counting signal edges of a signal generated from the reference signal the second counter outputting a second counter signal and a comparator is coupled to the first counter to receive the first counter signal and coupled to the second counter to receive the second counter signal, wherein the comparator generates a signal in the event the first counter signal is equal to the second counter signal, and the output of the comparator is coupled to reset the second counter.

The invention relates to a frequency multiplying device for determination of a fundamental frequency f of an analogue target signal. The device comprises a generating device for generating a reference signal having a frequency f.sub.osc, wherein f.sub.osc is greater than f, and a first counter being coupled to a terminal, the terminal to be fed with the analogue target signal, and being coupled to the generating device such that the first counter counts a number of signal edges generated from the reference signal in a time interval corresponding substantially to 1/f and outputs a first counter signal, wherein a frequency divider is coupled between the generating device and the first counter and a second counter is coupled to the generating device for counting signal edges of a signal generated from the reference signal the second counter outputting a second counter signal and a comparator is coupled to the first counter to receive the first counter signal and coupled to the second counter to receive the second counter signal, wherein the comparator generates a signal in the event the first counter signal is equal to the second counter signal, and the output of the comparator is coupled to reset the second counter.

Provided a method comprising: obtaining waveform data sets of a periodic electric waveform signal, with a length set to one cycle time; calculating a frequency spectrum for each waveform data set; extracting and separating odd and even frequency harmonics to create odd and even frequency harmonic matrices on which a canonical correlation analysis (CCA) being applied to obtain CCA features; performing linear transformation on the CCA features to obtain linear transformed features; generating a model based on the linear transformed features; performing magnitude quantization of frequency spectrums of waveform data sets to identify normal and anomalous waveform signals.

Provided a method comprising: obtaining waveform data sets of a periodic electric waveform signal, with a length set to one cycle time; calculating a frequency spectrum for each waveform data set; extracting and separating odd and even frequency harmonics to create odd and even frequency harmonic matrices on which a canonical correlation analysis (CCA) being applied to obtain CCA features; performing linear transformation on the CCA features to obtain linear transformed features; generating a model based on the linear transformed features; performing magnitude quantization of frequency spectrums of waveform data sets to identify normal and anomalous waveform signals.

A frequency counter circuit includes a first counter path to receive a digitally-controlled oscillator (DCO) clock signal and is configured to generate a first count corresponding to a first frequency of a first reduced clock signal corresponding to the DCO clock signal. A second counting path receives the DCO clock signal and generates a second count corresponding to a second frequency of a second reduced clock signal corresponding to the DCO clock signal. The first reduced clock signal is an integer multiple frequency of the second reduced clock signal. Detection circuitry detects a timing violation associated with the DCO clock signal based on a comparison between at least a portion of the first count and at least a portion of the second count.

A frequency counter circuit includes a first counter path to receive a digitally-controlled oscillator (DCO) clock signal and is configured to generate a first count corresponding to a first frequency of a first reduced clock signal corresponding to the DCO clock signal. A second counting path receives the DCO clock signal and generates a second count corresponding to a second frequency of a second reduced clock signal corresponding to the DCO clock signal. The first reduced clock signal is an integer multiple frequency of the second reduced clock signal. Detection circuitry detects a timing violation associated with the DCO clock signal based on a comparison between at least a portion of the first count and at least a portion of the second count.

A frequency estimator for estimating a frequency, including a counter configured to count an integer number of full clock cycles during a measurement time window; a Time-to-Digital Converter (TDC) configured to measure a fraction of a clock cycle during the measurement time window; and a processor configured to determine the estimated frequency based on the counted number of full clock cycles and the measured fraction of the clock cycle.

A period estimation apparatus includes processing circuitry configured to extract candidate periods being a target of period determination from an input pulse train, use at least one of the candidate periods extracted to determine whether the at least one of the candidate periods exists as an actual period, and, when determining that the at least one of the candidate periods does not exist as the actual period, suspend the period determination for the at least one of the candidate periods, perform the period determination for the at least one of the candidate periods determined to exist as the actual period, generate a pseudo periodic pulse train, adjust, based on a differential value between the pseudo periodic pulse train generated and the input pulse train, a pulse position of the pseudo periodic pulse train, and detect a periodic pulse train according to results of the period determination and adjustment.

A period estimation apparatus includes processing circuitry configured to extract candidate periods being a target of period determination from an input pulse train, use at least one of the candidate periods extracted to determine whether the at least one of the candidate periods exists as an actual period, and, when determining that the at least one of the candidate periods does not exist as the actual period, suspend the period determination for the at least one of the candidate periods, perform the period determination for the at least one of the candidate periods determined to exist as the actual period, generate a pseudo periodic pulse train, adjust, based on a differential value between the pseudo periodic pulse train generated and the input pulse train, a pulse position of the pseudo periodic pulse train, and detect a periodic pulse train according to results of the period determination and adjustment.

Disclosed are an apparatus for monitoring pulsed high-frequency power and a substrate processing apparatus including the same. The apparatus includes an attenuation module configured to attenuate a pulsed high-frequency power signal; a rectifier module configured to convert the pulsed high-frequency power signal into a direct current signal; and a detection module configured to detect a pulse parameter based on the direct current signal.