A resistance mapping device includes: a first chip including a first surface, a second surface positioned at a side opposite to the first surface, and a plurality of first electrodes provided at the first surface; a second chip including a third surface facing the first surface, a fourth surface positioned at a side opposite to the third surface, and a plurality of second electrodes provided at the third surface; and a measurement part, the measurement part being configured to measure a resistance of a portion of a measurement object, the portion of the measurement object being between the first electrode and the second electrode that correspond to each other among the plurality of first electrodes and the plurality of second electrodes, and acquire mapping data in which measured values of the resistances are associated with positions of the measurement object corresponding to the plurality of first electrodes.

A battery pack includes a plurality of cells and a control module. The control module is configured to acquire internal resistance of each of the plurality of cells, acquire a terminal voltage of each of the plurality of cells in real time in a case where the plurality of cells are charged with a constant current, determine an electromotive force of each of the plurality of cells based on the internal resistance of each of the plurality of cells and a charging current and the terminal voltage, determine a target cell from the plurality of cells based on the electromotive force of each of the plurality of cells, and perform charging balancing management on the target cell.

A battery pack includes a plurality of cells and a control module. The control module is configured to acquire internal resistance of each of the plurality of cells, acquire a terminal voltage of each of the plurality of cells in real time in a case where the plurality of cells are charged with a constant current, determine an electromotive force of each of the plurality of cells based on the internal resistance of each of the plurality of cells and a charging current and the terminal voltage, determine a target cell from the plurality of cells based on the electromotive force of each of the plurality of cells, and perform charging balancing management on the target cell.

A contact resistance test method and related devices are provided. When a MOS transistor working in a linear region is tested, a functional relationship between the channel width of the MOS transistor and total resistances of the MOS transistor at sampling temperatures is determined, to determine the contact resistance of the MOS transistor at the sampling temperatures. A calibration coefficient of the contact resistance at a current ambient temperature is determined based on the contact resistance of the MOS transistor at the sampling temperatures. A measurement result of the contact resistance is further adjusted based on the calibration coefficient of the contact resistance at the current ambient temperature, to obtain an accurate contact resistance at the current ambient temperature.

According to one embodiment, a sensor includes an element part, and a control circuit part. The element part includes first and second elements. Each of the first and second elements includes a first magnetic element and a first conductive member. The control circuit part includes a first current circuit, a differential circuit, and a phase detection circuit. The first current circuit is configured to supply a first current to the first conductive member. The differential circuit is configured to output a differential signal corresponding to a difference of a first signal and a second signal. The first signal corresponds to a change in a first electrical resistance of the first magnetic element of the first element. The second signal corresponds to a change in a second electrical resistance of the first magnetic element of the second element. The phase detection circuit is configured to perform a phase detection of the differential signal.

Apparatus having an array of memory cells and a controller for access of the array of memory cells, wherein the controller is configured to cause the apparatus to apply a reference current to a selected access line, determine a time difference between a voltage level of a near end of the selected access line being deemed to exceed a first voltage level while applying the reference current and the voltage level of the near end of the selected access line being deemed to exceed a second voltage level while applying the reference current, and determine a capacitance value of the selected access line in response to a current level of the reference current, the time difference, and a voltage difference between the second voltage level and the first voltage level.

Apparatus having an array of memory cells and a controller for access of the array of memory cells, wherein the controller is configured to cause the apparatus to apply a reference current to a selected access line, determine a time difference between a voltage level of a near end of the selected access line being deemed to exceed a first voltage level while applying the reference current and the voltage level of the near end of the selected access line being deemed to exceed a second voltage level while applying the reference current, and determine a capacitance value of the selected access line in response to a current level of the reference current, the time difference, and a voltage difference between the second voltage level and the first voltage level.

Circuits and methods that enable stacking of phase change material (PCM) switches and that accommodate variations in the resistance of the resistive heater(s) of such switches. Stacking is enabled by providing isolation switches for the resistive heater(s) in a PCM switch to reduce parasitic capacitance caused by the proximity of the resistive heater(s) to the PCM region of a PCM switch. Variations in the resistance of the resistive heater(s) of a PCM switch are mitigated or eliminated by sensing the actual resistance of the resistive heater(s) and then determining a suitable adjusted electrical pulse profile for the resistive heater(s) that generates a precise thermal pulse to the PCM region, thereby reliably achieving a desired switch state while extending the life of the resistive heater(s) and the phase-change material.

Circuits and methods that enable stacking of phase change material (PCM) switches and that accommodate variations in the resistance of the resistive heater(s) of such switches. Stacking is enabled by providing isolation switches for the resistive heater(s) in a PCM switch to reduce parasitic capacitance caused by the proximity of the resistive heater(s) to the PCM region of a PCM switch. Variations in the resistance of the resistive heater(s) of a PCM switch are mitigated or eliminated by sensing the actual resistance of the resistive heater(s) and then determining a suitable adjusted electrical pulse profile for the resistive heater(s) that generates a precise thermal pulse to the PCM region, thereby reliably achieving a desired switch state while extending the life of the resistive heater(s) and the phase-change material.

A uniformity property acquisition apparatus is the uniformity property acquisition apparatus configured to acquires a uniformity property of a mixture in which an insoluble solid matter is mixed in liquid, and the uniformity property acquisition apparatus includes: a pair of electrodes configured to apply the AC signal to the mixture; measurement unit configured to measure impedance of the mixture on the basis of a response signal flowing through the mixture when the AC signal is applied to the mixture; and processing unit configured to acquire the uniformity property of the mixture on the basis of the impedance measured by the measurement unit.