A fault detection circuit according to the present disclosure includes a rectangular pulse comparison circuit configured to generate, for each combination of the pulse width modulated signals, detection signals each indicating a difference component between pulse widths of two pulse width modulated signals having phases adjacent to each other, and a fault diagnosis unit configured to detect a fault in an inverter based on a shift in a combination of logic levels of a plurality of the detection signals output by the rectangular pulse comparison circuit from a preset determination value. The fault diagnosis unit uses the determination value that is different for each motor rotation angle assuming in advance that two alternating-current signals having phases adjacent to each other among the three-phase alternating-current signals have the same voltage.

A semiconductor device according to the present invention has a PLL circuit which includes: a phase comparison part that detects the phase difference between a reference signal and an oscillation signal to produce a phase difference signal indicative of the phase difference in binary and then output the produces signal to outside through a first external terminal; a voltage conversion part that applies, to a phase difference voltage node, a phase difference voltage having a voltage value corresponding to the phase difference represented by the phase difference signal; an oscillation part that produces, as an oscillation signal, a signal having a frequency depending on the phase difference voltage; and a correction circuit that supplies a correction current to the phase difference voltage node, and upon reception of a test control signal at a second external terminal, supplies a current depending on the test control signal to the phase difference voltage node as a correction current.

In accordance with some embodiments of the present invention, a method of adaptively operating a transmit detection circuit is presented. The method includes powering the transmit detection circuit with a capacitor charged by an LDO; receiving a digital ping signal from a transmitter; receiving a clock signal from a local oscillator; updating a register to accommodate timing of the digital ping signal; and generating a signal indicating whether the transmitter is present.

A hardware-in-the-loop (HIL) simulation device is provided, which includes a processing circuit and a pulse-width modulation (PWM) signal observation circuit. The PWM signal observation circuit includes an energy storage unit and the energy storage unit is coupled to the processing circuit. A signal source transmits a PWM signal to the processing circuit and the PWM signal observation circuit, and the energy storage unit is charged when the PWM signal is at high level. The processing circuit detects the voltage of the energy storage unit when detecting the falling edge of the PWM signal so as to calculate the duty cycle of the PWM signal.

A duty cycle measurement circuit obtains differential duty cycle measurements corresponding to the duty cycle of a signal at two or more different locations along a propagation path. The differential duty cycle measurements may include measurements of an input duty cycle and measurements of an output duty cycle. The duty cycle measurements may be acquired by use of duty-cycle-to-voltage converter circuitry. The duty cycle measurements may be used to determine a measure of the duty cycle deterioration of the propagation path, and an adjustment factor to compensate for the measured duty cycle deterioration.

A short-circuit protection and localization circuit for power devices includes a first subcircuit for detecting dv/dt of a power device at turn on, a second subcircuit for short-circuit fault localization and soft turn-off of the power device, the second subcircuit including a totem-pole driver having an upper switch and a lower switch, and a third subcircuit for detecting short-circuit faults based on the output (V.sub.dip) of the first subcircuit and the output of an upper switch (V.sub.p) of the second subcircuit. The first subcircuit outputs a voltage (V.sub.dip) having a magnitude that is proportional to dv/dt of the power device. The third subcircuit outputs a signal (V.sub.sto) to the second subcircuit that causes the second subcircuit to softly turn-off the power device. The second subcircuit outputs a voltage of the upper switch (V.sub.p) and a fault-latching signal for short-circuit localization.

Systems, methods, and circuits for determining a duty cycle of a periodic input signal are provided. A delay element is configured to delay the periodic input signal based on a digital control word. A digital circuit is configured to generate a first digital control word used to delay the periodic input signal a first amount of time corresponding to a period of the periodic input signal, generate a second digital control word used to delay the periodic input signal a second amount of time corresponding to a portion of the periodic input signal having a logic-level high value, and generate a third digital control word used to delay the periodic input signal a third amount of time corresponding to a portion of the periodic input signal having a logic-level low value. A controller is configured to determine the duty cycle based on the first, second, and third digital control words.

A power supply glitch detector includes a sense node AC coupled to a power supply node on which voltage glitches having a magnitude of V.sub.glitch are to be detected. A sensing inverter has an input and an output, the input coupled to the sensing node, the sensing inverter having a trip voltage V.sub.trip below which the output of the sensing inverter is at a voltage representing a logic high state and above which the output of the sensing inverter is at a voltage representing a logic low state. An adjustable voltage biasing circuit is coupled to the sensing node to maintain the input of the sensing inverter at a bias voltage V.sub.bias, wherein V.sub.bias is chosen such that either both conditions (V.sub.bias<V.sub.trip) and (V.sub.bias+V.sub.glitch>V.sub.trip) or both conditions (V.sub.bias>V.sub.trip) and (V.sub.biasV.sub.glitch<V.sub.trip) are always true.

An identification method is an identification method for use in an identification apparatus that identifies types of brushless DC motors each including a circuit board on which a terminal for tachometer is mounted. The duty ratios of pulses outputted from the terminals for tachometer vary among multiple types of brushless DC motors. The identification method includes: supplying a power supply voltage from the identification apparatus to a brushless DC motor; inputting pulses outputted from the terminal for tachometer of the circuit board to the identification apparatus; obtaining the duty ratio of the pulses as a unique information piece of the brushless DC motor; and identifying the type of the brushless DC motor based on the unique information piece of the brushless DC motor.

A power supply glitch detector includes a sense node AC coupled to a power supply node on which voltage glitches having a magnitude of V.sub.glitch are to be detected. A sensing inverter has an input and an output, the input coupled to the sensing node, the sensing inverter having a trip voltage V.sub.trip below which the output of the sensing inverter is at a voltage representing a logic high state and above which the output of the sensing inverter is at a voltage representing a logic low state. An adjustable voltage biasing circuit is coupled to the sensing node to maintain the input of the sensing inverter at a bias voltage V.sub.bias, wherein V.sub.bias is chosen such that either both conditions (V.sub.bias<V.sub.trip) and (V.sub.bias+V.sub.glitch>V.sub.trip) or both conditions (V.sub.bias>V.sub.trip) and (V.sub.biasV.sub.glitch<V.sub.trip) are always true.