A method of testing integrated circuit die for presence of a crack includes performing back end integrated circuit fabrication processes on a wafer having a plurality of integrated circuit die, the back end fabrication including an assembly process. The assembly process includes a) lowering a tip of a first manipulator arm to contact a given die such that pogo pins extending from the tip make electrical contact with conductive areas on the given die so that the pogo pins are electrically connected to a crack detector on the given die, b) picking up the given die using the first manipulator arm, and c) performing a conductivity test on the crack detector using the pogo pins to determine presence of a crack in the given die that extends from a periphery of the die, through a die seal ring of the die, and into an integrated circuit region of the die.

Test structures for a body-contacted field effect transistor (BCFET) include: a single-pad structure with body contact and probe pad regions connected to a channel region at first and second connection points with a known separation distance between the connection points; and a multi-pad structure with a body contact region connected to a channel region at a first connection point and multiple probe pad regions connected to the channel region at second connection points that are separated from the first connection point by different separation distances. A method includes: determining separation distance-dependent internal body potentials at the second connection points in response to different bias conditions by using either multiple single-pad structures, each having a different separation distance between the connection points, or by using a multi-pad structure; and based on the separation distance-dependent internal body potentials, generating a model representing the BCFET with body-contacted and floating body devices.

There is provided a maintenance apparatus including: an acquisition unit configured to acquire a plurality of test results, for each of a plurality of jigs, in a case where a plurality of devices under measurement, which are different from each other, are sequentially tested via the plurality of jigs; a calculation unit configured to calculate a variation in test results, for each jig, by using the plurality of test results; and a determination unit configured to determine maintenance timing of the jig based on the variation in the test results.

Provided are a failure diagnosis method and apparatus for open circuit failure of a power tube of a three-phase rectifier based on a current signal, relating to a failure diagnosis technique for power electronic equipment and capable of quickly and accurately diagnosing on an open circuit failure of the power tube of the three-phase rectifier without adding a hardware component. The failure diagnosis method only requires a sampled current existing in the control system of the rectifier and some intermediate computing signals and is therefore simple and requires little computing resource. A distorted current after the open circuit failure occurs in the power tube of the rectifier and a positive/negative half cycle where the current is present when the failure occurs serve as diagnostic variables. By analyzing the sampled current, a quick diagnosis on the power tube having the open circuit failure is provided. Thus, the invention is highly applicable.

In various examples, an inspection jig includes a plate-shaped insulating member having a recess; a first board having a first electrode; and a conducting wire electrically connected to a contact terminal. The insulating member is provided with a through hole penetrating a bottom portion of the recess. One end portion of the conducting wire is disposed in the through hole. The other end of the conducting wire is connected to the first electrode.

A data-driven misregistration parameter configuration and measurement system and method including simulating a plurality of measurement simulations of at least one multilayered semiconductor device, selected from a batch of multilayered semiconductor devices intended to be identical, using sets of measurement parameter configurations, generating simulation data for the device, identifying recommended measurement parameter configurations selected from sets of measurement parameter configurations, providing a multilayered semiconductor device selected from the batch, providing the at least one recommended set of measurement parameter configurations to a misregistration metrology tool having multiple possible sets of measurement parameter configurations, measuring at least one multilayered semiconductor device, selected from the batch, using the recommended set, thereby generating measurement data for the device, thereafter identifying a final recommended set of measurement parameter configurations and measuring misregistration of at least one multilayered semiconductor device, selected from the batch, using the final recommended set.

A semiconductor laser device (2) is placed on a first heating-cooling device (1). A probe holder (4) is attached on a second heating-cooling device (3), A measurement probe (8) is fixed to a distal end of the probe holder (4). A fine movement table (9) moves the second heating-cooling device (3) and the probe holder (4) so that a distal end of the measurement probe (8) contacts the semiconductor laser device (2). An inspection apparatus (10) inputs an inspection signal to the semiconductor laser device (2) through the measurement probe (8).

The invention relates to a porous thermoelectric material (5; 5a, 5b): having, at 20° C. and at atmospheric pressure, a thermal conductivity of less than 100 mW/(m.Math.K) and an electrical conductivity of between 20 S/m and 10.sup.5 S/m, and comprising a matrix of a thermal insulating material which has a porosity of more than 70%, and which may be filled at least locally with an electrically conductive material (5b), the content of the electrically conductive material being comprised between 0% and 90% by weight of the total weight of the thermal insulating material.

High power impedance tuners suffer from intense heating of the center conductor of the tuner airline (slabline), due to dissipated RF and DC power and, in addition to high electric field between the metallic tuning probe (slug) and the center conductor, also from associated thermal expansion causing sagging of the center conductor and possible electrical short. If the thermal expansion cannot be accommodated by structural means, the center conductor is cooled using forced air created by ventilators or re-circulating low loss dielectric liquid flowing through the slabline. Premature tuner aging through continuous airflow or cooling liquid circulation is avoided using real time monitoring of dissipated (heating) power and regulation of the cooling mechanism.

A chip removing apparatus for a repair process of a μLED display comprises: a stage unit on which a substrate having at least one chip arranged thereon is mounted; a film stage on which an adhesive film is mounted such that the adhesive film is located on the substrate; a head having a pin which pressurizes the adhesive film such that the chip is attached to the lower surface of the adhesive film; and a head driver for moving the head.