According to one embodiment, an inspection apparatus of a semiconductor device includes a first probe configured to contact a first portion of the semiconductor device, a conductive member configured to oppose a second portion of the semiconductor device, and a detector configured to apply a first voltage between the semiconductor device and the first probe, to apply a conductive member voltage between the semiconductor device and the conductive member, and to detect a current flowing in the first probe. The first voltage has a first polarity of one of positive or negative when referenced to a potential of the semiconductor device. The conductive member voltage has a second polarity of the other of positive or negative when referenced to the potential of the semiconductor device.

A testing circuit includes a first circuit and a second circuit. The first circuit and second circuit have a first capacitor and a second capacitor. The first circuit is connected to a first transistor. The second circuit is connected to a second transistor. A first inductor has a first terminal connected to an input of the testing circuit and a second terminal connected to a source of the second transistor. A first diode has an anode connected to ground and a cathode connected to the second terminal of the first inductor. The second capacitor has a first terminal connected to a drain of the second transistor and a second terminal connected to ground. The first capacitor has a first terminal connected to the input of the testing circuit and a second terminal connected to ground.

A semiconductor fabricating apparatus may include a probe card, a test head, a support and a chamber wall. The probe card may include a plurality of probing needles. The probe card may be installed at the test head. The support may be configured to receive a wafer including a plurality of test pads making contact with the probing needles. The chamber wall may be configured to receive the support. The chamber wall may define a chamber in which a probe test may be performed. At least one of the probe card and the support, the probe card and the test head, and the test head and the chamber wall may be combined with each other by a magnetic module.

The present application provides two-port on-wafer calibration piece circuit models and a method for determining parameters. The method includes: measuring a single-port on-wafer calibration piece circuit model corresponding to a first frequency band to obtain a first S parameter; calculating, according to the first S parameter, an intrinsic capacitance value of a two-port on-wafer calibration piece circuit model corresponding to the single-port on-wafer calibration piece circuit model; measuring the two-port on-wafer calibration piece circuit model corresponding to the terahertz frequency band to obtain a second S parameter; and calculating a parasitic capacitance value and a parasitic resistance value of the two-port on-wafer calibration piece circuit model according to the second S parameter and the intrinsic capacitance value.

An apparatus may include an upper transparent plate to hold a wafer of bottom-emitting or bottom-detecting optical devices, wherein the upper transparent plate comprises a set of holes in an area of the upper transparent plate for holding the wafer. The apparatus may include a lower transparent plate and a structure supporting the upper transparent plate and the lower transparent plate to form a cavity bounded by the upper transparent plate, the lower transparent plate, and the structure, wherein the structure comprises an opening in fluid communication with the cavity, wherein applying suction through the opening, via the cavity and the set of holes, holds the wafer flat on the upper transparent plate, and wherein an optical path, between a bottom-emitting or bottom-detecting optical device of the bottom-emitting or bottom-detecting optical devices of the wafer and a testing device, passes through the upper transparent plate, the cavity, and the lower transparent plate.

A semiconductor wafer evaluation apparatus brings a contact maker (mercury liquefied at room temperature), as a Schottky electrode, into contact with a semiconductor wafer, intermittently applies a voltage from a pulse power supply, and evaluates the state (kinds, density) of point defects by an evaluation means based on the status of the electrostatic capacity of the semiconductor wafer. In this manner, the state (kinds, density) of the point defects in the plane of a large-diameter semiconductor wafer is directly evaluated using a large table.

A probe card for testing power devices under high temperature and high voltage. The probe card includes air inlet system, PCB board, switching layer, guide plate and probe from top to bottom; the bottom of air inlet system includes plurality of lower air outlets and side air outlets, the PCB board includes a first through-hole with same position, shape and quantity as the lower air outlet, the switching layer includes a second through-hole with same position, shape and quantity as the lower air outlet, the guide plate includes a third through-hole with same position, shape and quantity as the lower air outlet. The lower air outlet, the first through-hole, the second through-hole and the third through-hole are coaxially arranged. The high-temperature and high-pressure gas ejected from the lower air outlet is blown between the guide plate and the tested wafer after successively passing through the first, second, and third through-holes.

Provided are a device and a method for monitoring substrates to determine a processed state of the substrates and inspecting presence of abnormality in the processed substrates. A device for inspecting substrates includes a substrate mounting part moving relative to the substrate and for mounting a substrate, a measurement part for monitoring the substrate, a control part configured to control a movement path of the measurement part so that at least some regions are monitored from positions different from each other with respect to a plurality of substrates, and an analysis part configured to determine presence of abnormality from monitoring information about the plurality of substrates.

A board-like connector, a dual-arm bridge of a board-like connector, and a wafer testing assembly are provided. The board-like connector includes a plurality of dual-arm bridges spaced apart from each other and an insulating layer. Each of the dual-arm bridges includes a carrier, a first cantilever, a second cantilever, a first abutting column, and a second abutting column, the latter two of which extend from the first and second cantilevers along two opposite directions. The first cantilever and the second cantilever extend from and are coplanar with the carrier. The insulating layer connects the carriers of the dual-arm bridges. The first abutting column and second abutting column of each of the dual-arm bridges respectively protrude from two opposite sides of the insulating layer, and are configured to abut against two boards, respectively.

A test and measurement instrument includes one or more processors to execute code to cause the processors to: access a user instance of the test and measurement instrument; receive one or more requests from the user instance of the test and measurement instrument; determine any collisions between the one or more requests and any other requests for elements of the test and measurement instrument; resolve any collisions as necessary; perform one or more operations to fulfill the request; and display information resulting from the one or more operations on an instance user interface.