A connecting device for electrically connecting signal contact portions of an electrical device under test includes a lower modular unit and an upper modular unit. The lower modular unit includes a port substrate and a plurality of lower connecting terminals electrically connected with the port substrate. The upper modular unit is disposed above the lower modular unit and includes a plurality of upper connecting terminals movable relative to an upper wall. The upper connecting terminals are movable as a result of a downward pressing of the electrical device to the upper modular unit to project outwardly of the upper wall and to electrically connect with the signal contact portions. The upper connecting terminals are electrically connected with the lower connecting terminals.

A semiconductor wafer comprising a first die including a first integrated circuit having a trimmable or programmable component. The trimmable or programmable component is configured to be trimmed or permanently altered in response to an electrical signal. The semiconductor wafer includes a second die arranged adjacent to the first die. The second die includes a second integrated circuit and at least one contact pad arranged to allow an electrical connection to be made to the second integrated circuit. The at least one contact pad is additionally electrically connected to the at least one trimmable or programmable component of the first die such that the at least one contact pad of the second die is configured to act as a probe pad.

A semiconductor test apparatus according to the present disclosure includes: a stage on which a wafer is to be mounted; a pressurizing wall disposed on a surface of a probe card opposing the stage, extending toward the stage, and having an opening; a mark disposed on a lower surface of the pressurizing wall opposing the stage; a probe disposed in the opening; an air tube to force air into the opening; a detector to detect first spacing between a tip of the probe and the mark; and a controller to control second spacing between the wafer and the lower surface of the pressurizing wall based on the first spacing, wherein, when an electrical property of each of chips of the wafer is measured, the second spacing is controlled to be predetermined spacing by the controller, and the air is forced into the opening through the air tube.

A circuital system that includes a differential low-pass filter having a differential output and operable in a first voltage domain. Some embodiments include a differential integrator including a differential input and a differential output, and operable in a second voltage domain different from the first voltage domain. Some embodiments include a pair of AC coupling capacitors coupling the differential output of the differential low-pass filter to the differential input of the differential integrator.

Provided are a parasitic capacitance detection method, a memory, and a readable storage medium, relating to the field of semiconductor technologies. The detection method comprises: providing a plurality of semiconductor devices for testing, all the semiconductor devices being the same in a number of sources, a number of drains, a number of active layers, a number of gates, a number of wires and a cross-sectional area of the wire, all the semiconductor devices being different in a length of the wire therein; determining a capacitance between the wire per unit length and the gate in the semiconductor device, the capacitance between the wire per unit length and the gate being considered as a parasitic capacitance per unit length; determining a corresponding wire length of a to-be-detected semiconductor device; and determining a parasitic capacitance of the to-be-detected semiconductor device.

Techniques for isolating interfaces while testing a semiconductor device include a semiconductor device having a link interface that couples the semiconductor device to a high-speed data transfer link, a clock control unit that transmits one or more clock signals to the link interface; and a protection module. The protection module asserts a clock stop request to the clock control unit and, in response to receiving a clock stop acknowledgement from the clock control unit, asserts a clamp enable to cause the link interface to be isolated from portions of the semiconductor device. After waiting for a first predetermined period of time to expire, the protection module de-asserts the clock stop request.

A circuital system that includes a differential low-pass filter having a differential output and operable in a first voltage domain. Some embodiments include a differential integrator including a differential input and a differential output, and operable in a second voltage domain different from the first voltage domain. Some embodiments include a pair of AC coupling capacitors coupling the differential output of the differential low-pass filter to the differential input of the differential integrator.

A dual-stage source measure unit (SMU) has a user interface to allow a user to input one or more target values, at least two terminals to couple to a device under test (DUT), a current loop having a current digital control loop (DCL), a current digital-to-analog converter (DAC), a sense resistor, a current analog-to digital converter (ADC), and a common ADC, the current DCL to receive inputs from the current ADC, from the common ADC, and a target value for the output current, and to control a first output stage to produce the output current, and a voltage loop having a voltage DCL, a voltage DAC, a voltage ADC, and the common ADC, the voltage DCL to receive inputs from the voltage ADC, from the common ADC, and a target value for the output voltage, and to control a second output stage to produce the output voltage.

The present disclosure provides a crack detection unit (CDU), a semiconductor die, and a method of detecting a crack of a semiconductor die. The CDU comprises a switching circuit, a crack sensor, and a logic circuit. The switching circuit is configured to enable the crack sensor. The crack sensor is configured to be electrically connected to the switching circuit, the ground, and an operating voltage. The logic circuit is configured to be electrically connected to the switching circuit and the crack sensor, wherein the CDU is enabled based on an input of the logic circuit. The output of the logic circuit indicates whether the crack sensor contains a crack.

An inspection apparatus for inspecting a semiconductor workpiece includes a testing stage, a first seal member, a testing clamp, a second seal member, a semiconductor workpiece, and a transducer. The testing stage has a cavity. The first seal member is disposed in the cavity. The first seal member is attached to a sidewall of the cavity. The testing clamp is movably coupled to the testing stage. The second seal member is attached to the testing clamp. The semiconductor workpiece is held between the testing stage and the testing clamp by the first seal member and the second seal member. The transducer is movably disposed above the testing stage.