Systems and methods for semiconductor adaptive testing using inline defect part average testing are configured to receive a plurality of inline defect part average testing (I-PAT) scores from an I-PAT system, where the plurality of I-PAT scores is generated by the I-PAT system based on semiconductor die data for a plurality of semiconductor dies, where the semiconductor die data includes characterization measurements for the plurality of semiconductor dies, where each I-PAT score of the plurality of I-PAT scores represents a weighted defectivity determined by the I-PAT system based on a characterization measurement of a corresponding semiconductor die of the plurality of semiconductor dies; apply one or more rules to the plurality of I-PAT scores during a dynamic decision-making process; and generate one or more adaptive tests for at least one semiconductor die of the plurality of semiconductor dies based on the dynamic decision-making process.

An inspection device includes a reference signal output section, a noise removal section, and an electrical characteristic measurement section. The reference signal output section is connected to an external power supply device in electrical parallel with a semiconductor sample, and outputs a reference signal according to the output of the external power supply device. The noise removal section outputs a noise removal signal obtained by removing a noise component of the output of the external power supply device from the current signal output from the semiconductor sample based on the reference signal. The electrical characteristic measurement section measures the electrical characteristic of the semiconductor sample based on the noise removal signal. The inspection device measures the electrical characteristic of the semiconductor sample to which a voltage is being applied by the external power supply device and which is being irradiated and scanned with light. The inspection device outputs a defective portion of the semiconductor sample based on the electrical characteristic.

The present disclosure provides a method of analyzing a semiconductor device. The method includes providing a first transistor, a second transistor disposed adjacent to the first transistor, and a gate electrode common to the first transistor and the second transistor; connecting a power-supply voltage (V.sub.dd) to the gate electrode to turn on the first transistor, determining a first threshold voltage (V.sub.th) based on the power-supply voltage; switching the power-supply voltage to a ground voltage (V.sub.ss); connecting the ground voltage to the gate electrode to turn on the second transistor; and determining a second threshold voltage based on the ground voltage.

An inspection device according to an embodiment can conduct high temperature inspection and low temperature inspection on an object to be inspected. The inspection device includes an inspection chamber in which inspection is conducted on the object; a dry air supply section that is connected to the inspection chamber via a first valve and that is configured to supply dry air into the inspection chamber; a dew point meter that is connected to the inspection chamber via a second valve and that is configured to measure a dew point in the inspection chamber; and a bypass pipe connecting the dry air supply section and the dew point meter via a third valve.

A fault detection circuit includes a short circuit comparison circuit which has a first input connected to the source of the second NFET, a second input, and an output. The circuit includes an over-current comparison circuit which has a first input connected to the source of the second NFET, a second input, and an output. The circuit includes a voltage divider circuit which has a first terminal connected to first input of the short circuit comparison circuit, a second terminal connected to the first input of the over-current comparison circuit, and a third terminal connected to a ground terminal. The circuit includes a delay circuit which has an input connected to the output of the over-current comparison circuit and has an output.

A thermal measurement system includes a temperature-controlled chamber configured to house a Device Under Test (DUT) and a first temperature sensor to measure an external temperature of the DUT inside the temperature-controlled chamber. The thermal measurement system further includes a heating device for heating a test material outside the temperature-controlled chamber and a controller configured to control the heating device to heat the test material to the external temperature measured by the first temperature sensor of the DUT inside the temperature-controlled chamber. In one aspect, a thermethesiometer indicates a skin effect of a surface temperature of the test material outside the temperature-controlled chamber.

A wafer inspection system and a wafer inspection equipment thereof are provided. The wafer inspection system includes a susceptor device, probe card, and bridge module. The susceptor device includes a susceptor unit for placing a wafer under test. The probe card includes a probing portion and conducting portion. The conducting portion is disposed at the periphery of the probing portion and has a contact surface. The bridge module includes transmission units extended upward, positioned adjacent to a wafer placement area, and coupled to the susceptor unit. When the probing portion comes into contact with a testing point of the wafer, the contact surface of the conducting portion gets coupled to the transmission units to transmit a test signal to the probe card via the transmission units and conducting portion and thus form a test loop. Thus, the test loop path can be shortened and the accuracy of signal transmission and inspection can be enhanced.

A semiconductor structure includes: a through silicon via penetrating a base; and a protection structure, including: a conductive first test ring and a conductive second test ring both arranged around the through silicon via and electrically insulated from the through silicon via; a first dielectric layer located between the first test ring and the second test ring and configured to electrically isolate the first test ring from the second test ring; and a first connection layer located in the first dielectric layer and configured to be electrically connected to the first test ring and the second test ring.

A method for instantaneous load pull impedance pattern generation uses a phase-frequency-location equivalent of the natural behavior of slide screw tuners to skew the reflection factor phase with only small frequency changes. The method is generic and applies the same to all GHz range test frequencies. A simple calculation determines the tuning probe position and the impedance cloud is generated quasi instantaneously by switching between sidebands of the carrier test frequency without mechanically moving the tuning probe. Benign frequency behavior of the tuners allows for simple and accurate narrowband interpolation. Duration of load pull measurements is reduced from minutes to seconds.

The multilayer test sample includes a stack with a bottom layer, a top layer, and a tunnel layer sandwiched between the bottom and top layers. The multilayer test sample has terminals below the stack for measuring on the stack. The terminals have unknown positions or distance between them. A model and a measurement strategy is defined so that material parameters of the stack may be determined.