In this testing device, a space in which a transistor 117 is disposed and a space in which a driving circuit for testing is disposed are separated by a partition wall 214. The driving circuit has a plurality of switch circuit boards 201, and a conductive plate 204 for connection is attached to the switch circuit board 201. A fork plug 205e is connected to a collector c terminal of the transistor 117 to be tested, and a fork plug 205c is connected to an emitter e terminal. The insertion of the fork plug 205 into an opening 216 provided in the partition wall 214 allows the connection of the fork plug 205 and the conductive plate 204. By changing the position of the opening 216 for inserting the fork plug 205, the connection to the driving circuit can be changed in accordance with an item to be tested.

A circuit board for semiconductor test includes first and second sub-circuit boards, and an insulating dielectric layer therebetween. Each sub-circuit board includes a substrate and circuits including upper and lower contacts. The insulating dielectric layer includes through holes, and connecting conductors disposed therein and electrically connected with the upper and lower contacts of two sub-circuit boards. The circuit board is defined with central and peripheral regions. The lower contacts of the first sub-circuit board in the central region are electrically connected with a probe head. The upper contacts of the second sub-circuit board in the peripheral region are electrically connected with a tester, larger in pitch than the lower contacts of the first sub-circuit board in the central region, and larger in amount than the lower contacts of the first sub-circuit board in the peripheral region. The circuit board has great power test uniformity.

An electronic device inspection apparatus of the present application comprises an inspection table for positioning and holding an electrode disposed on a semiconductor device , a contact element that is formed of a shape memory alloy in a long and thin plate shape and has a base part fixed to the inspection table and a variable part formed in a shape of a spiral at a first temperature and being developed from the spiral at a second temperature; and a measurement circuitry for measuring the semiconductor device by conducting a current to flow into the electrode via the contact element. The axis of the spiral of the variable part is parallel to the electrode face of the positioned electrode and a contact region is formed along a longitudinal direction between the variable part and the positioned electrode at the second temperature.

A system to detect gate-open failures in a MOS based insulated gate transistor can include a detection circuit, including a first circuit configured to measure a drain-source voltage across the MOS based insulated gate transistor, a first comparator circuit can be configured to compare the measured drain-source voltage to a threshold drain-source conduction voltage indicating a conduction state of a channel of the MOS based insulated gate transistor, a second circuit can be configured to measure a gate voltage applied at a gate of the MOS-based insulated gate transistor, a second comparator circuit can be configured to compare the gate voltage applied at the gate to a threshold gate voltage for the MOS based insulated gate transistor to provide an indication of whether the gate voltage applied at the gate is sufficient to activate conduction in the channel and a logic circuit can be configured to detect a gate-open failure of the MOS based insulated gate transistor based on the conduction state of the channel and the indication of whether the gate voltage applied at the gate is sufficient to activate conduction in the channel when the MOS based insulated gate transistor is in an on state or an off state.

A testing apparatus for measuring a strength of a chip includes: a cassette mounting base on which to mount a cassette capable of accommodating wafer units; a frame fixing mechanism that fixes an annular frame of the wafer unit; a conveying mechanism that conveys the wafer unit between the cassette and the frame fixing mechanism; a pushing-up mechanism that pushes up a predetermined chip included in the wafer supported by the annular frame fixed by the frame fixing mechanism; a pick-up mechanism having a collet picking up the chip pushed up by the pushing-up mechanism; a strength measuring mechanism having a support unit supporting the chip picked up by the collet; and a collet moving mechanism that moves the collect from a position facing the pushing-up mechanism to a position facing the support unit.

Embodiments according to the invention can provide methods of testing a SiC MOSFET, that can include applying first and second voltage levels across a gate-source junction of a SiC MOSFET and measuring first and second voltage drops across a reverse body diode included in the SiC MOSFET responsive to the first and second voltage levels, respectively, to provide an indication of a degradation of a gate oxide of the SiC MOSFET and an indication of contact resistance of the SiC MOSFET, respectively.

The disclosure describes an apparatus for testing a component, wherein the apparatus is configured to apply a magnetic field with a magnetic field orientation from a set of magnetic field orientations to the component. The apparatus is further configured to perform a test on the component in the presence of the respective magnetic fields with the respective magnetic field orientations from the set of magnetic field orientations to obtain an information characterizing an operation of the component. The apparatus is also configured to determine a test result based on the information characterizing the operation of the component in the presence of different magnetic fields with different magnetic field orientations from the set of magnetic field orientations. The disclosure also describes a method of testing and a computer-readable storage device for implementing the method and provides more efficiency in view of reliability and costs.

A method for monitoring an online state of a bonding wire of an Insulated Gate Bipolar Translator (IGBT) module comprises the following steps: Step 1, constructing a full bridge inverter circuit and an online measuring circuit and connecting two input ends of the online measuring circuit to a collecting electrode and an emitting electrode of an IGBT power module of the full bridge inverter circuit to realize a connection of the full bridge inverter circuit and the online measuring circuit; Step 2, establishing a three-dimensional data model of a healthy IGBT; Step 3, establishing a three-dimensional data model of the IGBT with a broken bonding wire; Step 4, optimizing a least squares support vector machine by adopting a genetic algorithm; and Step 5, estimating states of the three-dimensional data models obtained in the Step 2 and the Step 3 by utilizing the optimized least squares support vector machine.

A pull out-assisting linkage device for load board of semiconductor automatic test equipment. One end of the handle is rotatably connected to the test equipment by a rotating member. The middle of the handle is bolted to the linkage. The two rotating plates are fixedly connected to the linkage and are located at the two ends of the linkage. Each rotating plate is rotatably connected to the test equipment. Both the first pull out-assisting rod and the second pull out-assisting rod are fixedly connected to each rotating plate by a universal connecting rod. The first pull out-assisting rod and the second pull out-assisting rod are slidingly connected to the test equipment. The first pull out-assisting rod has a first pull out-assisting slot in the side wall, and the second pull out-assisting rod has a second pull out-assisting slot in the side wall, with the first pull out-assisting slot and the second pull out-assisting slot set in reverse. The present invention makes the pull out-assisting device more accurate in propulsion distance, simple in structure, and low in investment cost.

A fault detection circuit includes a short circuit comparison circuit which has a first input connected to the source of the second NFET, a second input, and an output. The circuit includes an over-current comparison circuit which has a first input connected to the source of the second NFET, a second input, and an output. The circuit includes a voltage divider circuit which has a first terminal connected to first input of the short circuit comparison circuit, a second terminal connected to the first input of the over-current comparison circuit, and a third terminal connected to a ground terminal. The circuit includes a delay circuit which has an input connected to the output of the over-current comparison circuit and has an output.