Provided is a test method of a semiconductor apparatus comprising: first testing the semiconductor apparatus by bringing one or more probe pins into contact with a pad of the semiconductor apparatus; and second testing the semiconductor apparatus in a state where contact positions of the one or more probe pins with respect to the pad are different from those of the first testing. In the first testing, the one or more probe pins may be brought into contact with first positions and second positions on the pad, and in the second testing, the one or more probe pins may be brought into contact between the first positions and the second positions on the pad.

Reliability test macros for contact over active gate (COAG) layout designs are provided. In one aspect, a COAG layout design reliability test macro includes: gate-shaped dielectric structures disposed over an active area of a substrate; source/drain regions present on opposite sides of the gate-shaped dielectric structures; source/drain contacts in direct contact with the source/drain regions; a dielectric fill material disposed on the source/drain contacts; and gate contacts present over, and in direct contact with, the gate-shaped dielectric structures in the active area, wherein the dielectric fill material is present in between the gate contacts and the source/drain contacts. Methods of forming and using the present COAG layout design reliability test macros are also provided.

Embodiments of the present invention provide systems and methods for multidimensional parts average testing for testing devices and analyzing testing results to detect outliers according to embodiments of the present invention. The testing can include calculating multivariate (e.g., bivariate) statistics using delta measurements of like devices, a ratio of measurements, or principal component analysis that identifies eigenvectors and eigenvalues to define meta parameters, for example. Raw test result data can be converted to residual space and robust regression can be performed to prevent outlier results from influencing regression, thereby reducing overkill advantageously.

A test head assembly for a semiconductor device has a carrier, a pin seat and a test wire assembly. The carrier is formed in an L shape and has a lateral board, a perpendicular board and a opening formed through the perpendicular board. The pin seat is mounted in the corresponding opening. The test wire assembly has a teat head, a plurality of connectors and a plurality of test wires. The test head is mounted on an outer sidewall of the lateral board and connected to the pin seat through the test wires and the connectors. Therefore, the pin seat is mounted on the perpendicular board of the L-shaped uprightly and the test head is mounted on the lateral board. The pin seat and the test head are not parallel to each other, and a lateral size of the test head assembly is reduced to increase the space usage.

A method for detecting defects in a GaN high electron mobility transistor is disclosed. The method includes steps of measuring a plurality of electrical characteristics of a GaN high electron mobility transistor, measuring the plurality of electrical characteristics after performing a deterioration test on the GaN high electron mobility transistor, irradiating the GaN high electron mobility transistor in turns with a plurality of light sources with different wavelengths and measuring the plurality of electrical characteristics after each irradiation of the GaN high electron mobility transistor by each of the plurality of light sources, and comparing changes of the plurality of electrical characteristics measured in the above steps to determine the defect location of the GaN high electron mobility transistor.

A semiconductor test apparatus according to the present disclosure includes: a stage on which a wafer is to be mounted; a pressurizing wall disposed on a surface of a probe card opposing the stage, extending toward the stage, and having an opening; a mark disposed on a lower surface of the pressurizing wall opposing the stage; a probe disposed in the opening; an air tube to force air into the opening; a detector to detect first spacing between a tip of the probe and the mark; and a controller to control second spacing between the wafer and the lower surface of the pressurizing wall based on the first spacing, wherein, when an electrical property of each of chips of the wafer is measured, the second spacing is controlled to be predetermined spacing by the controller, and the air is forced into the opening through the air tube.

A method of operating an electrical test prediction apparatus includes determining a relationship between first electrical test (ET) data, corresponding to at least one shot region comprising a subset of a plurality of semiconductor chips of a wafer, and electrical die sorting (EDS) data, obtained by measuring a state of each chip on the wafer by a testing device, and predicting second ET data, corresponding to an region of the wafer other than the at least one shot region by performing machine learning on the relationship.

A model parameter test structure for a transistor includes: a substrate, having a first conductivity type, a plurality of isolation structures being provided in the substrate and the isolation structures being used to isolate different doped regions; a first test device, formed in the substrate and configured to obtain characteristic parameters of a source side of the transistor; and a second test device, formed in the substrate and configured to obtain characteristic parameters of a drain side of the transistor; wherein a structure of the first test device is different from a structure of the second test device.

A circuital system that includes a differential low-pass filter having a differential output and operable in a first voltage domain. Some embodiments include a differential integrator including a differential input and a differential output, and operable in a second voltage domain different from the first voltage domain. Some embodiments include a pair of AC coupling capacitors coupling the differential output of the differential low-pass filter to the differential input of the differential integrator.

A method for checking the operation of a photovoltaic module of a photovoltaic power station. The module has a positive terminal, a negative terminal and a number of solar cells, in particular thin-layer solar cells. An electric field emitted by the photovoltaic module as a result of solar radiation is measured at an exposed measurement location during the operation of the power station and the electrical voltage present between the positive terminal and the negative terminal is determined from the measured electric field. A corresponding measuring instrument has a sensor to be placed near the photovoltaic module so as to measure the electric field strength. A rod or wand may be used to position the sensor, or a robot may be configured for automatic travel on the photovoltaic module.