A device having at least one power semiconductor die coated with a metallization and at least one light guide having two opposite ends. The first end is able to be connected at least to a light source and to a light receiver. The second end is permanently fixed facing to a surface of the metallization such that to form a light path towards said surface and a light path from said surface.

A method and device for monitoring a multi-die power module in a half-bridge switch configuration are provided. The method and device are designed to set dies in a non conductive state, select one die which is blocking a voltage, inject a current in a gate of the selected die in order to charge an input parasitic capacitance of the selected die, monitor a voltage that is representative of a voltage on the gate of the selected die, and memorize the value of the monitored voltage when the value of the monitored voltage is stabilized.

A carrier lifetime measurement method for measuring a lifetime of carriers in a measurement target object includes an irradiation step of irradiating a DUT 10 serving as a measurement target object with measurement light and stimulus light subjected to intensity modulation using a plurality of frequencies, an outputting step of outputting a detection signal by detecting an intensity of reflected light from the DUT 10 or transmitted light through the DUT 10, and a generation step of detecting a phase delay of the detection signal with respect to a modulation signal including a frequency in association with a concentration of impurities in a measurement target region of the plurality of frequencies and generating image data indicating a distribution of lifetimes of carriers in the DUT 10 on the basis of the phase delay.

The disclosure discloses an IGBT module reliability evaluation method and device based on bonding wire degradation, which belong to the field of IGBT reliability evaluation. The realization of the method includes: obtaining a relationship between a IGBT chip conduction voltage drop U.sub.ces and an operating current I.sub.c along with a chip junction temperature T.sub.c; for an IGBT module under test, obtaining the conduction voltage drop U.sub.ces-c of the IGBT chip through the operating current I.sub.c and the chip junction temperature T.sub.c; obtaining an external conduction voltage drop U.sub.ces-m of the IGBT module by using a voltmeter; performing subtraction to obtain a voltage drop at a junction of a IGBT chip and a bonding wire, and combining the operating current to obtain a resistance at the junction; determining that the IGBT module has failed when the resistance at the junction increases to 5% of an equivalent impedance of the IGBT module.

Embodiments of the present application provide an evaluation method for hot carrier effect degraded performance, which includes: providing at least one wordline and at least one wordline driver; performing an electrical test on the wordline; performing a characteristic test on a sample passing the electrical test, to obtain a first performance parameter; inputting an AC signal to an input end of the wordline driver, to control the wordline to be repeatedly on and off through the wordline driver; performing the electrical test on the wordline; and performing the characteristic test on the sample passing the electrical test, to obtain a second performance parameter, and evaluating the hot carrier effect degraded performance of the wordline driver according to the first performance parameter and the second performance parameter.

An apparatus including a set of one or more receivers; a first replica circuit being a substantial replica of at least a portion of one of the set of one or more receivers; a first control circuit generates an output signal selectively coupled to an input of the first replica circuit; a second replica circuit being a substantial replica of at least a portion of one of the set of one or more receivers; a comparator including a first input coupled to a first output of the first replica circuit, a second input coupled to a second output of the second replica circuit, and an output; and a second control circuit including an input coupled to the output of the comparator, and an output coupled to the first replica circuit and to the set of one or more receivers.

The apparatus for ESD test includes a micro-controller unit client, a low voltage supply configured to output a low voltage on the basis of control by the micro-controller unit, a high voltage supply configured to output a high voltage on the basis of control by the micro-controller unit, and an ESD generator configured to generate an ESD voltage for an ESD test of a device under test (DUT) by using the low voltage and the high voltage, on the basis of control by the micro-controller unit. The ESD generator is a semiconductor integrated circuit module where a charging semiconductor switch, a discharging semiconductor switch, a switch driving block controlling a switching operation of each of the charging semiconductor switch and the discharging semiconductor switch, and a plurality of passive elements connected to the charging semiconductor switch and the discharging semiconductor switch are implemented as package, for generating the ESD voltage.

Techniques for usage metering by bias temperature instability with differential sensing on pairs of matching transistors are provided. In one aspect, a usage metering device includes: at least one metering circuit on a chip, the at least one metering circuit having a pair of matching transistors, and a differential current sense circuit connected to the pair of matching transistors, wherein the pair of matching transistors includes a reference transistor which is unused during regular operation of the chip, and a stressed transistor that is on continuously during the regular operation of the chip, and wherein the differential current sense circuit determines a Vt difference between the reference transistor and the stressed transistor. A method for usage metering and a method of forming a usage metering device are also provided.

A compressor, a monitoring system and a method of monitoring a compressor that make it possible to monitor the remaining lifetime of a semiconductor element of a motor control system while the processing load is reduced are provided. A compressor (1) includes: a motor control system (10) that controls the rotation speed of a motor (2); a compressor body (3) that compresses air by being driven by the motor (2); a pressure sensor (20) that is provided on the discharge side of the compressor body (3); and a running controller (11) that performs switching between load running and no-load running on the basis of the pressure sensed by the pressure sensor (20). A motor controller (26) of the motor control system (10) calculates a relative temperature of a semiconductor element relative to a reference temperature by using a temperature of the semiconductor element sensed by a temperature sensor (27) at the time of switching from no-load running to load running, and calculates an amount of change in a remaining lifetime of the semiconductor element corresponding to the relative temperature of the semiconductor element, whereby monitoring the remaining lifetime of the semiconductor element.

The present disclosure provides a method and a system for testing semiconductor device. The method includes providing a device under test (DUT) having an input terminal and an output terminal; applying a voltage having a first voltage level to the input terminal of the DUT during a first period; applying a stress signal to the input terminal of the DUT during a second period subsequent to the first period; obtaining an output signal in response to the stress signal at the output terminal of the DUT; and comparing the output signal with the stress signal. The stress signal includes a plurality of sequences, each having a ramp-up stage and a ramp-down stage. The stress signal has a second voltage level and a third voltage level.