A device comprising at least one power semiconductor die coated with a metallization and at least one light guide having two opposite ends. The first end is able to be connected at least to a light source and to a light receiver. The second end is permanently fixed facing to a surface of the metallization such that to form a light path towards said surface and a light path from said surface.

Provided are a semiconductor device and a method of operating the same. A semiconductor includes a test circuit which comprises: a test transistor to be tested for time-dependent dielectric breakdown (TDDB) characteristics using a stress voltage; an input switch disposed between a voltage application node to which the stress voltage is applied and an input node which transmits the stress voltage to the test transistor; and a protection switch disposed between the input node and a ground node.

A thermally conductive material, device, and method for predictably maintaining the temperature state and condition of the contact elements and support hardware of a tester interface, such as a probe card, for a testing apparatus, such as automated test equipment (ATE), that has a predetermined configuration applicable for the particular pin contact elements, thermal conditions. The thermally conductive device also has a substrate having a predefined form factor which can be readily introduced into the testing apparatus during normal testing operations. Unlike a patterned substrate that is constrained to specific probe element layouts, the unpatterned surface of the heat conductive device facilitates use with multiple probe card designs within numerous automated test equipment (ATE) tools.

A process and system for testing includes: arranging devices in a temperature-controlled environment; applying a negative gate bias voltage (Vgs) to the devices; applying a drain voltage (Vds) to the devices; measuring currents and/or voltages of the devices to generate device test data; determining a failure of one or more of the devices based on the device test data generated from the device currents and/or the voltages to generate failure data; and outputting the failure data for the of devices.

The present disclosure provides a method and a system for testing semiconductor device. The method includes providing a device under test (DUT) having an input terminal and an output terminal; applying a voltage having a first voltage level to the input terminal of the DUT during a first period; applying a stress signal to the input terminal of the DUT during a second period subsequent to the first period; obtaining an output signal in response to the stress signal at the output terminal of the DUT; and comparing the output signal with the stress signal. The stress signal includes a plurality of sequences, each having a ramp-up stage and a ramp-down stage. The stress signal has a second voltage level and a third voltage level.

A semiconductor device may include: first to n-th through-electrodes; first to n-th through-electrode driving circuits suitable for charging the first to n-th through-electrodes to a first voltage level, or discharging the first to n-th through-electrodes to a second voltage level; and first to n-th error detection circuits, each suitable for storing the first voltage level or the second voltage level of a corresponding through-electrode of the first to n-th through-electrodes as a down-detection signal and an up-detection signal, and outputting a corresponding error detection signal of first to n-th error detection signals by sequentially masking the down-detection signal and the up-detection signal.

A diagnostic system for a power conversion apparatus including a semiconductor device and performing a switching operation for carrying and interrupting a main current to a main current is disclosed. This system includes a trigger circuit that acquires reference time for the switching operation; and a delay time calculation circuit that acquires first time at which the main current takes a first main current set value and second time at which the main current takes a second main current set value, and that detects numerical data about a difference between the first time and the reference time and numerical data about a difference between the second time and the reference time.

A method for predicting yield for a semiconductor process. A particular type of wafer is fabricated to have a first set of features disposed on the wafer, with a wafer map identifying a location for each of the first set of features on the wafer. Data from wafer acceptance tests and circuit probe tests is collected over time for wafers of that particular type as made in a semiconductor fabrication process, and at least one training dataset and a least one validation dataset are created from the collected data. A second set of “engineered” features are created and also incorporated onto the wafer and wafer map. Important features from the first and second sets of features are identified and selected, and using those important features as inputs, a number of different process models are run, with yield as the target. The results of the different models can be combined, for example, statistically.

Disclosed are a reliability test fixture and an online test device for a flexible display component. The fixture comprises a support and a rotating shaft rotatably mounted on the support. An engagement recess for fixing a flexible display component is provided in an axial direction on the surface of the rotating shaft. A test module used to detect an electrical parameter of an internal circuit of the flexible display component is disposed inside the rotating shaft. The test module has a test contact for electrically connecting to the flexible display component. During a test, the flexible display component is fixed in the engagement recess and is electrically connected to the test module.

A method for assessing the state of damage of a semiconductor module that is subject to operational loading, in particular a semiconductor module of a drive system converter, that includes at least one semiconductor component arranged on or in a support structure. It is possible not only to estimate a spent service life for the entire semiconductor module, but also to detect unexpected or undesirable loading states and thus a premature reduction of the remaining service life of the semiconductor module. Continuous load assessments are thus possible already during the operation of the semiconductor module and allow interventions to be made in good time.