A method for generating an aging model used in the design of a semiconductor chip includes: extracting a plurality of aging scenarios including a use condition of the semiconductor chip from an aging model library of the semiconductor chip; calculating a first aging parameter commonly applied to a plurality of semiconductor elements included in the semiconductor chip from the plurality of aging scenarios; and generating characteristic deterioration information due to aging of each of the semiconductor elements through simulation using the first aging parameter and a second aging parameter of each of the semiconductor elements.

A method for selecting components in a radiation tolerant electronic system, comprising, determining ionizing radiation responses of COTS devices under various radiation conditions, selecting a subset of the COTS devices whose radiation responses satisfy threshold radiation levels, applying mathematical models of the COTS devices for post-irradiation conditions to determine radiation responses to ionizing radiation; implementing a radiation-tolerant architecture using COTS devices from the selected subset, the implemented circuit may be tested for robustness to ionizing radiation effects without repeated destructive tests of the hardware circuit by using the mathematical models for simulating response to the ionizing radiation, and implementing a multi-layer shielding to protect the implemented circuit under various radiation conditions.

Embodiments are directed to a system for measuring a degradation characteristic of a plurality of electronic components. The system includes a parallel stress generator communicatively coupled to the plurality of electronic components, and a serial electronic measuring component communicatively coupled to the plurality of electronic components. The parallel stress generator is configured to generate a plurality of stress signals, apply the plurality of stress signals in parallel to the plurality of electronic components and remove the plurality of stress signals from the plurality of electronic components. The serial electronic measuring component is configured to, subsequent to the removal of the plurality of stress signals, sequentially measure the degradation characteristic of each one of the plurality of electronic components in order to determine their degradation resulting from the applied stress signals.

Techniques regarding determining device operability via a metal-induced layer exchange are provided. For example, one or more embodiments described herein can comprise an apparatus, which can comprise a dielectric membrane positioned between an amorphous semiconductor resistor layer and an electrically conductive metal layer. The dielectric membrane can facilitate a metal induced layer exchange that can experiences catalyzation by heat generated from operation of a semiconductor device positioned adjacent to the apparatus.

Disclosed are a test chamber and a test apparatus having the same. The test chamber includes a test compartment configured to support a plurality of test boards, each being configured to secure a test object. The test chamber applies a test signal to the test object. The test chamber includes an inlet side and a discharge side, and a supply duct vertically extending along a height of the test compartment. The supply duct supplies the inlet side of the test compartment with the test fluid. The test chamber includes a fluid controller to uniformly control a distribution of a test fluid in the supply duct and uniformly supply the test compartment with the test fluid. The disclosed test chamber and test apparatus provide a uniform test temperature and thereby improve a test reliability of a test object such as a semiconductor or semiconductor package.

A ring oscillator test circuit, includes an odd number of stages, where each stage includes a load and drive transistor connected in series at a common node. The common node of each stage is electrically connected to the drive transistor gate of the following stage, and the common node of the last stage is connected to the drive transistor gate of the first stage. A first voltage input connects to the drains of all the load transistors. A second voltage input connects to the gates of all of the load transistors. A reference voltage input connects to the sources of all of the drive transistors. At least one of the common nodes connects to a test output.

Embodiments of the invention are directed to a semiconductor wafer test system. A non-limiting example of the test system includes a controller, a sensing system communicatively coupled to the controller, and a stress source communicatively coupled to the controller. The controller is configured to control the stress source to deliver an applied stress to a targeted stress area of a semiconductor wafer. The sensing system is configured to detect the applied stress and provide data of the applied stress to the controller. The controller is further configured to control the stress source based at least in part on the data of the applied stress.

A fault detection method includes, at a generator module having a generator, a rectifier connected to the generator by phase leads, and an inverter connected to the rectifier by a direct current (DC) link, receiving a measurement of voltage applied to the rectifier by the phase leads and receiving a measurement of voltage applied to the inverter by the DC link. DC link voltage balance and sequence voltages are calculated using the measurement of voltage applied to the rectifier by the phase leads and the measurement of voltage applied to the inverter by the DC link. Determination is made using the DC link voltage balance and phase sequence voltages when no fault exists in the generator module. Determination is made that a fault condition exists using the DC link voltage balance and phase sequence voltages when a fault exists in the generator module. Generator modules are also described.

Embodiments of the invention are directed to a semiconductor wafer test system. A non-limiting example of the test system includes a controller, a sensing system communicatively coupled to the controller, and a stress source communicatively coupled to the controller. The controller is configured to control the stress source to deliver an applied stress to a targeted stress area of a semiconductor wafer. The sensing system is configured to detect the applied stress and provide data of the applied stress to the controller. The controller is further configured to control the stress source based at least in part on the data of the applied stress.

An object of the invention is to provide the semiconductor module which can predict a life precisely, and the life prediction system for the semiconductor module. The semiconductor module according to the present invention includes IGBTs, diodes, measurement circuits for measuring characteristics of the IGBTs and the diodes, and a memory for storing initial values of predetermined characteristics of the IGBTs and the diodes, measured values of characteristics of the IGBTs and the diodes measured by measurement circuits, and a predetermined determination value for characteristic degradation of the IGBTs and the diodes.