A method and device estimate life consumption for an electronic component for use with an electric motor. The method and device allow maximal/minimal temperature values of semiconductor devices to be continuously monitored to allow on-cycle thermal damage and post-cycle damage to be determined in a parallel manner.

The present application relates to a test circuit, comprising: M stages of test units, first terminals of test units in each stage being all connected to a power wire, second terminals of test units in each stage being all connected to a ground wire, third terminals of test units in the first stage being connected to the power wire, and third terminals of test units in the i.sup.th stage being connected to fourth terminals of test units in the (i−1).sup.th stage; wherein, the M and i are positive integers greater than or equal to 2.

The present application relates to a test circuit, comprising: M test units, each test unit having a first terminal and a second terminal, a first terminal of each test unit being connected to a power wire, a second terminal of each test unit being connected to a ground wire, M being a positive integer; each test unit comprises a TDDB test component, a switch, and a control circuit; the TDDB test component has a first equivalent resistance before being broken down, the TDDB test component has a second equivalent resistance after being broken down, and the first equivalent resistance is greater than the second equivalent resistance.

A system to detect gate-open failures in a MOS based insulated gate transistor can include a detection circuit, including a first circuit configured to measure a drain-source voltage across the MOS based insulated gate transistor, a first comparator circuit can be configured to compare the measured drain-source voltage to a threshold drain-source conduction voltage indicating a conduction state of a channel of the MOS based insulated gate transistor, a second circuit can be configured to measure a gate voltage applied at a gate of the MOS-based insulated gate transistor, a second comparator circuit can be configured to compare the gate voltage applied at the gate to a threshold gate voltage for the MOS based insulated gate transistor to provide an indication of whether the gate voltage applied at the gate is sufficient to activate conduction in the channel and a logic circuit can be configured to detect a gate-open failure of the MOS based insulated gate transistor based on the conduction state of the channel and the indication of whether the gate voltage applied at the gate is sufficient to activate conduction in the channel when the MOS based insulated gate transistor is in an on state or an off state.

Embodiments of a degradation phenomenon treatment method based on a photovoltaic module and a related device are disclosed. A high frequency signal is applied to the photovoltaic module when a degradation phenomenon occurs in the photovoltaic module to protect the photovoltaic module and suppress or eliminate the degradation phenomenon. The degradation phenomenon refers to degradation of electricity generation efficiency of the photovoltaic module under effect of an electric potential. Embodiments of the degradation phenomenon treatment method and the device resolve issues associated with a declined electrical energy conversion capability and decreased electricity generation efficiency of a photovoltaic module caused by a surface polarization phenomenon, a potential induced degradation (PID) phenomenon occurring in the photovoltaic module, or both.

A method analyzes an operation of a power semiconductor device. The method includes: providing a set of reference voltages of the device and a set of corresponding reference currents; measuring, within a predetermined time-interval, Nframe on-state voltages and Nframe corresponding on-state currents of the device to obtain Nframe measurement points, Nframe being an integer number equal to or greater than 2; adapting the set of reference voltages by carrying out a least squares fit to the Nframe measurement points; and using the adapted set of reference voltages to analyze the operation of the power semiconductor device.

Provided are a semiconductor device and a method of operating the same. A semiconductor includes a test circuit which comprises: a test transistor to be tested for time-dependent dielectric breakdown (TDDB) characteristics using a stress voltage; an input switch disposed between a voltage application node to which the stress voltage is applied and an input node which transmits the stress voltage to the test transistor; and a protection switch disposed between the input node and a ground node.

A semiconductor device may include: first to n-th through-electrodes; first to n-th through-electrode driving circuits suitable for charging the first to n-th through-electrodes to a first voltage level, or discharging the first to n-th through-electrodes to a second voltage level; and first to n-th error detection circuits, each suitable for storing the first voltage level or the second voltage level of a corresponding through-electrode of the first to n-th through-electrodes as a down-detection signal and an up-detection signal, and outputting a corresponding error detection signal of first to n-th error detection signals by sequentially masking the down-detection signal and the up-detection signal.

A method and system for predicting an insulated gate bipolar transistor (IGBT) lifetime based on compound failure mode coupling are provided. First, a simultaneous failure probability model of a bonding wire and a solder layer is calculated. Next, expectancy of the simultaneous failure probability model is calculated and recorded as a lifetime under a coupling effect. A coupling function relation is established. A lifetime of the solder layer and a lifetime of the bonding wire are predicted. An IGBT lifetime prediction model not taking the coupling effect into account is established. An IGBT lifetime prediction model taking the coupling effect into account is established. In the disclosure, the lifetime of the IGBT module under the coupling effect of the solder layer and the bonding wire may be accurately predicted.

An integrated circuit die includes a core fabric configurable to include an aging measurement circuit and a device manager coupled to the core fabric to operate the aging measurement circuit for a select period of time. The aging measurement circuit includes a counter to count transitions of a signal propagating through the aging measurement circuit during the select period of time when the aging measurement circuit is operating. The transitions of the signal counted by the counter during the select period of time are a measure of an aging characteristic of the integrated circuit die.