An apparatus is described for burn-in and/or functional testing of microelectronic circuits of unsingulated wafers. A large number of power, ground, and signal connections can be made to a large number of contacts on a wafer. The apparatus has a cartridge that allows for fanning-in of electric paths. A distribution board has a plurality of interfaces that are strategically positioned to provide a dense configuration. The interfaces are connected through flexible attachments to an array of first connector modules. Each one of the first connector modules can be independently connected to a respective one of a plurality of second connector modules, thereby reducing stresses on a frame of the apparatus. Further features include for example a piston that allows for tight control of forces exerted by terminals onto contacts of a wafer.

An information output apparatus includes: a first switching element joined through a solder part, and forming one arm of a power conversion apparatus; a second switching element connected in series with the first switching element, and forming the other arm of the power conversion apparatus; a smoothing capacitor; a measuring unit configured to measure a temperature of the first switching element to output a measured value; an applying unit configured to apply two or more continuous pulses in a state where a potential difference across the smoothing capacitor is greater than or equal to a predetermined value, the pulses causing the first switching element and the second switching element to simultaneously turn on; an adjusting unit configured to adjust pulse widths of the pulses; and an output unit configured to output information indicating a deterioration of the solder part based on a manner of a change in measured values.

A contact for burning-in and testing a semiconductor IC and a socket device including the contact are proposed. The contact includes: an upper terminal part (111) having an upper tip part (111b) at an upper end part thereof; a lower terminal part (112) having a lower tip part (112c) at a lower end part thereof and provided on the same axis as the upper terminal part (111); and an elastic part (113) elastically supporting the upper terminal part (111) and the lower terminal part (112), wherein the upper terminal part (111) and the lower terminal part (112) include a shoulder part (111a) and a shoulder part (112a), respectively, formed by protruding therefrom in width directions thereof, and the elastic part (113) has a third width (w3), and includes a first strip (113a) and a second strip (113b).

A method of analyzing defects in a semiconductor device includes: collecting current data by applying a test voltage to the semiconductor device; extracting data within a decrease range from the current data; dividing the current data into a first component value and a second component value using the current data and the data extracted from within the decrease range; calculating a first quality index from the first component value satisfying a first function; and calculating a second quality index from the second component value satisfying a second function that is different from the first function.

A method for predicting high-temperature operating life of an integrated circuit (IC) includes performing bias temperature instability tests and high-temperature operating life tests on a device of the IC, establishing a relationship between the device bias temperature instability and the IC's high-temperature operating life based on a result of the bias temperature instability tests and the high-temperature operating life tests. The method further includes providing a lot of subsequent integrated circuits (ICs), performing wafer-level bias temperature instability tests on a device of the ICs, and predicting high-temperature operating life of the ICs based on a result of the wafer-level bias temperature instability tests and based on the established relationship between the device's bias temperature instability and the IC's high-temperature operating life. The method can save significant effort and time over conventional approaches for accurate prediction of high-temperature operating life of an IC.

An abnormality measuring method and an abnormality measuring apparatus of equipment are provided. The abnormality measuring method includes the following steps: acquiring a feature sequence corresponding to a life cycle according to recipe information and sensing information, wherein the feature sequence includes a plurality of feature subset sequences, and the life cycle is relative to a plurality of process runs; performing repeatedly a life segment analyzing process to acquire a plurality of life segments of the life cycle and each of the plurality of the feature subset sequences corresponding to one of the plurality of life segments; building a corresponding trending distribution of each of the plurality of life segments according to a corresponding feature subset sequence of the life segment; and determining whether to send an alarm message according to a plurality of trending distributions.

Probe systems and methods including active environmental control are disclosed herein. The methods include placing a substrate, which includes a device under test (DUT), on a support surface of a chuck. The support surface extends within a measurement environment that is at least partially surrounded by a measurement chamber. The methods further include determining a variable associated with a moisture content of the measurement environment and receiving a temperature associated with the measurement environment. The methods also include supplying a purge gas stream to the measurement chamber at a purge gas flow rate and selectively varying the purge gas flow rate such that a dew point temperature of the measurement environment is within a target dew point temperature range. The methods further include providing a test signal to the DUT and receiving a resultant signal from the DUT. The systems include probe systems that perform the methods.

A flexible probe card according to the present invention includes a compression layer; a transport layer coupled to the compression layer; and a contact layer coupled to the transport layer. The compression layer is formed of encapsulated closed cell polyurethane foam. The transport layer includes connectors for coupling the flexible probe card to a tester. The contact interface layer includes embedded conductive wires placed in a fixed grid pattern in a silicon rubber layer without a specific connector pattern associated either with the transport layer or a device under test.

A method for detecting the aging of a power electronic device that comprises at least one semiconductor component including a step of providing of an excitation signal, which is designed to trigger a flow of an at least approximately semi-sinusoidal excitation current through the semiconductor component in order to introduce a power loss into the semiconductor component, a step of uploading a temperature signal, which represents the temporal course of the temperature of the semiconductor component, and a step of determining of an aging value that represents the aging of the power electronic device by using the temperature signal.

Systems and methods of detecting non-uniform aging and degradation of power assembly units are disclosed. The system may include a first power assembly unit and a second power assembly unit adjacent to the first power assembly unit. Each of the first and second power assembly units has a coupling capacitor and a number of electrical components. The system may further include a current sensor in between the coupling capacitors of the first and second power assembly units to detect a current spike in the coupling capacitors and the electrical components.