An electronic-component testing device capable of achieving efficient heat-releasing from a self-heating electronic component and efficiently performing a desired test while maintaining the temperature of the electronic component in a predetermined range higher than ordinary temperature.

Embodiments are directed to a system for measuring a degradation characteristic of a plurality of electronic components. The system includes a parallel stress generator communicatively coupled to the plurality of electronic components, and a serial electronic measuring component communicatively coupled to the plurality of electronic components. The parallel stress generator is configured to generate a plurality of stress signals, apply the plurality of stress signals in parallel to the plurality of electronic components and remove the plurality of stress signals from the plurality of electronic components. The serial electronic measuring component is configured to, subsequent to the removal of the plurality of stress signals, sequentially measure the degradation characteristic of each one of the plurality of electronic components in order to determine their degradation resulting from the applied stress signals.

An apparatus provides precision measurement of voltage drop across a semiconductor switching element of a subsea device. The apparatus includes (a) a first circuit path having a first protective element, a first impedance element and a voltage source, wherein the first circuit path is configured to be connected between the first terminal and the second terminal of the semiconductor switching element, (b) a second circuit path formed between a first output terminal and a second output terminal, the second circuit path having a second protective element and a second impedance element, wherein the second protective element is identical to the first protective element, and wherein the second impedance element is identical to the first impedance element, and (c) a regulating circuit configured to regulating the current in the second circuit path such that said current in the second circuit path is equal to the current in the first circuit path, wherein the voltage drop between the first terminal and the second terminal of the semiconductor switching element equals the difference between the voltage provided by the voltage source and the voltage drop between the first output terminal and the second output terminal.

A test apparatus includes a tray including at least a first region and a second region, and a cap disposed over the tray. The cap includes a cap body, and at least a first magnet and a second magnet disposed over the cap body. The first magnet is configured to provide a first magnetic field to the first region of the tray, and the second magnet is configured to provide a second magnetic field to the second region of the tray. A strength of the first magnetic field is different from a strength of the second magnetic field.

A method for determining the remaining usability of a semiconductor module in normal use. The semiconductor module is thermally coupled to a cooling device. A predefined electrical load is applied to the semiconductor module while predefined cooling is effected by the cooling device. A temperature of a semiconductor element of the semiconductor module is sensed at least for the predefined electrical load on the semiconductor module. The sensed temperature is compared with a comparison temperature in a first comparison. The comparison temperature is assigned to the predefined electrical load with the predefined cooling, and prediction data for the remaining usability of the semiconductor module in normal use up to a usability end are determined at least in accordance with the first comparison.

A method for testing a lifetime of a surface state carrier of a semiconductor, including the following steps, 1) a narrow pulse light source is used to emit a light pulse, and coupled to an interior of a near-field optical probe, and the near-field optical probe produces a photon-generated carrier on a surface of a semiconductor material under test through excitation. 2) The excited photon-generated carrier is concentrated on the surface of the semiconductor material, and recombination is conducted continuously with a surface state as a recombination center. 3) A change in a lattice constant is produced due to an electronic volume effect, a stress wave is produced, and a signal of the stress wave is detected in a high-frequency broadband ultrasonic testing mode. 4) Fitting calculation is conducted on the signal of the stress wave to obtain the lifetime of the surface state carrier τ.sub.c.

A method of analyzing defects in a semiconductor device includes: collecting current data by applying a test voltage to the semiconductor device; extracting data within a decrease range from the current data; dividing the current data into a first component value and a second component value using the current data and the data extracted from within the decrease range; calculating a first quality index from the first component value satisfying a first function; and calculating a second quality index from the second component value satisfying a second function that is different from the first function.

A method of monitoring a condition of a SiC MOSFET can include (a) applying a first test gate-source voltage across a gate-source of a SiC MOSFET in-situ, the first test gate-source voltage configured to operate the SiC MOSFET in saturation mode to generate a first drain current in the SiC MOSFET, (b) applying a second test gate-source voltage across the gate-source of the SiC MOSFET in-situ, the second test gate-source voltage configured to operate the SiC MOSFET in fully-on mode to generate a second drain current in the SiC MOSFET, (c) determining a drain-source saturation resistance using the first drain current to provide an indication of a degradation of a gate oxide of the SiC MOSFET; and (d) determining a drain-source on resistance using the second drain current to provide an indication of a degradation of contact resistance of the SiC MOSFET.

The present application discloses a method and apparatus for calculating the kink current of SOI device, which is used to solve the problem that the kink current calculation in the prior art is not accurate and is not suitable for circuit simulation. The method includes: obtaining the impact ionization factor, the parasitic transistor effect factor, and the drain saturation current of the SOI device respectively; and calculating the kink current of the SOI device according to the impact ionization factor, the parasitic transistor effect factor, and the drain saturation current.

A substrate support includes a supporting unit and a light irradiation mechanism. The supporting unit includes a plate member on which an inspection target is placed and a transparent member. The light irradiation mechanism is configured to irradiate light to increase a temperature of the inspection target. Each of the plate member and the transparent member is made of a low thermal expansion material having a linear expansion coefficient of 1.0×10.sup.−6/K or less.