A method for selecting components in a radiation tolerant electronic system, comprising, determining ionizing radiation responses of COTS devices under various radiation conditions, selecting a subset of the COTS devices whose radiation responses satisfy threshold radiation levels, applying mathematical models of the COTS devices for post-irradiation conditions to determine radiation responses to ionizing radiation; implementing a radiation-tolerant architecture using COTS devices from the selected subset, the implemented circuit may be tested for robustness to ionizing radiation effects without repeated destructive tests of the hardware circuit by using the mathematical models for simulating response to the ionizing radiation, and implementing a multi-layer shielding to protect the implemented circuit under various radiation conditions.

Provided are a semiconductor device and a method of operating the same. A semiconductor includes a test circuit which comprises: a test transistor to be tested for time-dependent dielectric breakdown (TDDB) characteristics using a stress voltage; an input switch disposed between a voltage application node to which the stress voltage is applied and an input node which transmits the stress voltage to the test transistor; and a protection switch disposed between the input node and a ground node.

Systems and methods are disclosed for IC fabrication by specifying a process monitor with one or more functional blocks including process monitoring structures and wafer identification and die location data on the wafer; fabricating the functional blocks embedded in the wafer at one or more die locations; capturing functional test measurements during or after fabricating the functional blocks; and predicting device failures based on information of known device failures or related process parameters and their relationship to functional test measurements.

Disclosed are a test chamber and a test apparatus having the same. The test chamber includes a test compartment configured to support a plurality of test boards, each being configured to secure a test object. The test chamber applies a test signal to the test object. The test chamber includes an inlet side and a discharge side, and a supply duct vertically extending along a height of the test compartment. The supply duct supplies the inlet side of the test compartment with the test fluid. The test chamber includes a fluid controller to uniformly control a distribution of a test fluid in the supply duct and uniformly supply the test compartment with the test fluid. The disclosed test chamber and test apparatus provide a uniform test temperature and thereby improve a test reliability of a test object such as a semiconductor or semiconductor package.

According to one aspect of the present disclosure, a transport system includes a mobile cassette unit capable of storing a plurality of structures and supplying the structures to an inspection unit, wherein each of the structures includes a substrate on which a plurality of devices are formed, and an interconnect member including a contact section that electrically contacts an electrode of the plurality of devices.

A contact for burning-in and testing a semiconductor IC and a socket device including the contact are proposed. The contact includes: an upper terminal part (111) having an upper tip part (111b) at an upper end part thereof; a lower terminal part (112) having a lower tip part (112c) at a lower end part thereof and provided on the same axis as the upper terminal part (111); and an elastic part (113) elastically supporting the upper terminal part (111) and the lower terminal part (112), wherein the upper terminal part (111) and the lower terminal part (112) include a shoulder part (111a) and a shoulder part (112a), respectively, formed by protruding therefrom in width directions thereof, and the elastic part (113) has a third width (w3), and includes a first strip (113a) and a second strip (113b).

Embodiments of the present application provide a testing equipment and a testing method. The testing equipment includes: a plurality of pad groups and a plurality of source measure units. Each of the pad groups has a stress pad. The stress pad is configured to connect an element under test. The source measure unit is configured to send an input signal to the element under test through the stress pad and measure an output signal of the element under test to acquire performance parameters of the element under test. The stress pads of at least two of the pad groups are connected to the corresponding source measure units at the same time. The embodiments of the present application help improve the testing efficiency.

Laser-assisted integrated circuit (IC) device testing apparatus capable of inducing hot carrier injection (HCI) within selected transistors of an IC device. A laser source of sufficiently high output power (e.g., 1W) and short pulse duration (e.g., 100 fs) can generate enough hot carriers through a multi-photon (e.g., TPA) carrier injection mechanism to significantly accelerate HCI aging even at low transistor voltage bias (e.g., <1.5V). Rapid laser-assisted HCI transistor aging can selectively degrade transistors of individual functional IC blocks within an IC device.

A method for estimating the aging of an electronic component, characterized in that it includes the following steps: —compiling a thermal specification of the electronic component in order to determine a reference lifetime, —determining a reference temperature quantity, —measuring the actual temperature of the electronic component in operation, —determining an actual temperature quantity, —determining an equivalent operating time at the actual temperature, —transposing this equivalent operating time to the reference temperature to obtain a transposed operating time, —summing the transposed operating times to obtain a consumed lifetime comparable to the reference lifetime.

An increased accuracy in detecting deterioration of a semiconductor device can be achieved. A first metal pattern and a second metal pattern are connected to a controller. A bonding wire connects the first metal pattern and an emitter electrode. A linear conductor is connected between a first electrode pad and a second electrode pad. First bonding wires connect the first electrode pad and the second metal pattern. Second bonding wires connect the second electrode pad and the second metal pattern. The controller detects the deterioration of the semiconductor device when a potential difference between the first metal pattern and the second metal pattern is above a threshold.